Cache handling device in multi-channel multi-phase filter

Abstract

The invention discloses a cache handling device in a multi-channel multi-phase filter. The cache handling device comprises a control module, a BRAM (Block Random Access Memory), a triggering module, a plurality of registers, a plurality of coefficient memories and a plurality of cascaded DSP (Digital Signal Processor) modules, wherein the quantities of the registers, the coefficient memories and the DSP modules are the same, and each stage of DSP module corresponds to different registers and coefficient memories. According to the invention, two output ports of the BRAM are used for outputting data to the DSP modules, coefficients are stored in independent coefficient memories, and only logical resources are consumed during realization; the plurality of additionally arranged registers are used for storing data output by the output ports of the BRAM, so as to achieve multi-phase processing, at the moment, each output port of the BRAM can provide cache service for the plurality of DSP modules; and therefore, the cache handling device provided by the invention can be used to make the best of the BRAM, thereby reducing the use amount of the BRAM and saving the BRAM resource.

Description

technical field [0001] The invention relates to the filter field, in particular to a buffer processing device in a multi-channel polyphase filter. Background technique [0002] In a Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) system, the baseband rate is 1.28M and there are many channels. For example, 2-antenna F-band 12 carriers, a total of 2*12*2=48 channels; 8-antenna A-band 9 carriers, a total of 8*9*2=144 channels, the number of general channels is 24 or 48 Integer multiples of . [0003] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) in the selection of high-end platform, the operating frequency is set to 245.76M, with 48 channels as the basic unit; in the selection of low-end platform, the operating frequency is set to 122.88M , with 24 channels as the basic unit. In the above two cases, the structure is the same, but the number of channels is different. The first case is taken as an example below to describe in detail. ...

AI Technical Summary

Problems solved by technology

There are following shortcomings in the utilization of BRAM: (1) in order to multiply with 4 different coefficients, the data that the first port outputs to the DSP module just changes once every 4 clock cycles, and there is time redundancy; (2) The control logic used to generate by the second port is only some address information, which is not complicated, and the coefficients generated at the same time are also fixed.

Therefore, if one BRAM corresponds to one DSP, more BRAMs will be used, but each BRAM will not be fully utilized, resulting in a waste of BRAM resources.

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