A screening test method for fpga embedded multiplier

Abstract

The invention relates to a performance testing method of an FPGA embedded multiplier, comprising the following steps: (1) IP core function design of the embedded multiplier; (2) pseudo-random sequence test vector design; (3) RTL-level code simulation; ( 4) Test result analysis circuit design; (5) Module replication and output logic design. The screening test method of the FPGA embedded multiplier provided by the present invention adopts the test method based on BIST, which solves the shortcomings of high ATE test cost and difficult test technology; at the same time, the pseudo-random sequence is used as the stimulus input, which reduces the test time. Improved testing efficiency. This method makes full use of the programmable characteristics of the FPGA chip, as well as the abundant programmable logic units and embedded memory units (Block Random Access Memory, BRAM) inside the chip. The invention has simple implementation steps, strong portability and certain engineering application value.

Description

technical field [0001] The invention relates to a screening and testing method for an FPGA embedded multiplier, belonging to the technical field of integrated circuits. Background technique [0002] With the development of technical fields such as computer, information technology and integrated circuit design, digital signal processing has become increasingly important in various fields due to its advantages such as high precision, high flexibility, easy large-scale integration and multi-dimensional data processing. come out. Digital signal processing system is the carrier of digital signal processing, and its core component is digital signal processing unit. FPGA is a typical representative of reconfigurable digital processing unit. It stands out from the digital processing units and is favored by more and more users. [0003] Field Programmable Gate Arrays (Field Programmable Gate Arrays, FPGA) generally integrate dozens or even hundreds of embedded multiplier modules. T...

AI Technical Summary

Problems solved by technology

[0006] (1) It requires expensive expenses to purchase or rent ATE equipment, and needs to develop specific ATE test procedures, which increases the cost that users need to bear to a certain extent

[0007] (2) With the continuous increase of FPGA integration, chip functions become more and more complex, and the number of packaged I / O ports is limited, it is becoming more and more difficult to use ATE equipment to comprehensively test FPGA internal resources

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