Object Detection Hardware Accelerator and Acceleration Method

Abstract

The present invention relates to the field of data processing, and provides a target detection hardware accelerator and an acceleration method. The accelerator includes a convolution operator integrated with a multiplier and an adder, and the convolution operator receives volumes stored in block random access memory in advance. Product weight data and feature maps, the multiplier performs multiplication operations on the convolution weight data and feature maps to obtain multiplication result data and convolution offset data, and the adder performs multiplication result data and convolution offset data The data is shifted, added and summed to obtain the multiplication and accumulation result data; the pooling operation unit is used to receive the multiplication and accumulation result data and perform a pooling operation, and output the pooling result data; the RBR operation unit is used to perform the multiplication and accumulation result data; The pooling result data is subjected to batch normalization and quantization to obtain target feature data and stored in the block random access memory. The invention can reduce the time and power consumption required by the accelerator for data transfer, and improve the working efficiency of the accelerator.

Description

technical field [0001] The invention relates to the field of data processing, in particular to an object detection hardware accelerator and an acceleration method. Background technique [0002] With the support of big data analysis and large-scale high-speed computing platform, neural network technology has been developed sufficiently. On the one hand, neural network algorithms continue to improve. After CNN (Convolutional Neural Networks, convolutional neural network), new network models such as RNN (Recurrent Neural Network, cyclic neural network) and GAN (Generative Adversarial Networks, generative confrontation network) emerge in endlessly. ; On the other hand, due to the outstanding performance of neural network algorithms in the fields of image recognition, speech analysis and natural language processing, they are widely used in embedded systems. An embedded system is a dedicated system on a chip, which has strict requirements on system performance and power consumpti...

AI Technical Summary

Problems solved by technology

However, most of the existing neural network accelerators use DRAM to read data in the process of data transfer, which needs to be transmitted through the bus. The bandwidth of the bus is limited, and the power consumption and delay of reading a large amount of data from DRAM are very large. Greatly reduces the working efficiency of the accelerator

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