Circuit structure for implementing alternative of messages

Abstract

The invention discloses a circuit structure for implementing alternative of messages. The circuit structure comprises an alternative judgment logic module, a judgment waiting buffer module, a current SEQID (SEQuence IDentifier) buffer module, and a scanning logic module, wherein the judgment waiting buffer module and the current SEQID buffer module are connected with the alternative judgment logic module; the scanning logic module is connected with the judgment waiting buffer module; an inlet of the alternative judgment logic module is connected with two selecting and receiving channels; and messages of two selecting and receiving channels are from dual-transmitter messages of the same source equipment. The circuit structure for implementing alternative of the messages, which is disclosed by the invention, adopts the independent alternative judgment logic module and judgment waiting buffer module, so that functions of the respective modules are relatively single, and the circuit structure is convenient to implement a logic circuit; and moreover, the judgment waiting buffer module is managed in an RAM (SDP BLOCK RAM) multiplexing mode, so that a great quantity of judgment waiting buffer module control resources are saved, and a message group number of an alternative circuit can support a range to 1K (1024) and even more.

Description

technical field [0001] The invention belongs to the technical field of smart grids, and in particular relates to a circuit structure for realizing message selection. Background technique [0002] In some cases where the packet processing bandwidth is very small, it is a relatively simple way to use software programming to select one of the two packets, such as figure 1 Shown: The FPGA chip is used to provide 4 Ethernet ports, two of which are used as the entrance of the selective receiving channel, one is used as the interconnection channel between the FPGA chip and the CPU, and the other is used as the output channel of the selective receiving result. After receiving the message from the selective receiving channel, the FPGA adds a channel mark to the message by encapsulating the outer VLAN, and the modified message is forwarded to the CPU from the internal interconnection port, and the upper layer software of the CPU can extract the selective receiving message from the bot...

AI Technical Summary

Problems solved by technology

[0004] 1. In the case of large bandwidth, the software cannot process at wire speed;

[0005] 2. Low reliability

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