Embedded independent dual-port BRAM (block RAM) IP hardcore of FPGA (field programmable gate array)

Abstract

The invention belongs to the technical field of an FPGA (field programmable gate array), and particularly relates to an embedded independent dual-port BRAM (block RAM) IP hardcore of an FPGA. According to the embedded independent dual-port BRAM IP hardcore, a circuit simulation delay control module is introduced into a module, and the transmission delay of circuit signals under different process angles, working temperatures and voltages is obtained through dynamic simulation and fed back to a pulse generation module for control so as to improve the asynchronous time sequence control reliability of overall design. Moreover, the static leakage power consumption is reduced by use of a high-threshold tube SRAM; by optimizing the size of a transmission gate of the SRAM, the drive capability of a bit-line pull-up module is reduced, and the dynamic power consumption caused by mutual pull of drive sources is lowered, so that the power consumption of the BRAM IP hardcore is remarkably reduced. By adopting the BRAM IP hardcore provided by the invention, the programmable storage resource supported by the Block RAM can be applied more widely.

Description

technical field [0001] The invention belongs to the field of FPGA technology, and in particular relates to the design and realization of an IP hard core of an independent dual-port Block RAM with high reliability and low power consumption in the FPGA. Background technique [0002] The introduction of IP hard cores such as Block RAM and DSP into FPGA, which is widely used in digital circuit design and verification, can solve the problem of performance and functional limitations of logic resources in FPGA, so that FPGA can better support large-scale applications in digital circuit design. size, high speed, and power consumption optimization requirements. [0003] Block RAM (hereinafter referred to as BRAM) is a circuit module widely used in electronic systems, mainly used to support large-scale data storage and exchange in design. Although the idea of ​​embedding BRAM into FPGA has been realized for a long time, few studies are based on optimizing the embedded hard core itsel...

AI Technical Summary

Problems solved by technology

For traditional BRAM, due to its large storage capacity and the asynchronous complexity of internal control signal transmission, it has become a constraint for FPGA applications in terms of speed and reliability for control signals and data with long transmission distances. factor

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