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Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism

A technology for node processing and implementation methods, which is applied to the application of error detection coding of multiple parity bits, error correction/detection using block codes, data representation error detection/correction, etc., to achieve less hardware resources and high throughput , strong practical effect

Active Publication Date: 2013-07-24
XIAN INSTITUE OF SPACE RADIO TECH
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

This method changes the structure of the parity check matrix, and can only be used for a certain type of QC-LDPC code with a specific structure

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  • Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism
  • Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism
  • Realization method for QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving node processing parallelism

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Embodiment 1

[0080] Using the design method of the QC-LDPC decoder proposed by this patent to improve the parallelism of node processing, the present invention will be described in detail below taking LDPC (8176, 7154) as an example.

[0081] Such as figure 2 As shown, LDPC(8176,7154) is a QC-LDPC code (that is, a quasi-cyclic shift LDPC code), and its parity check matrix is ​​composed of 2×16 L×L (L=511) circulant matrices. The check matrix size is M×N=1022×8176, A i,j is a 511×511 circular matrix, A i,j There are two non-zero elements in each row and column of , that is, A i,j The row weight of is 2, so the row weight of the check matrix is ​​2×16=32, and the column weight is 2×2=4. The check matrix structure is as follows:

[0082] A 1,1 A 1,2 . . . ...

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Abstract

The invention relates to a realization method for a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoder for improving the node processing parallelism. The decoder comprises a variable node information updating unit (VNU), a variable node information packing unit (VP), a check node information updating unit (CNU), a check node information packing unit (CP), a check equation computing unit (PCU), storage blocks RAM (Random Access Memory)_f and RAM_m with storage bit widths of (Qh)bits respectively and a storage block RAM_c with the storage bit width of hbits. According to the realization method disclosed by the invention, due to the adoption of the node information packing unit, simultaneous reading and writing of batch data of a memory can be effectively realized and the problem of access conflict of the memory is solved; and the number of data stored in each address unit of the memory is added, so that the parallelism of a processing unit of the LDPC decoder can be improved. The realization method for the QC-LDPC decoder has the characteristics of high throughput capacity, fewer hardware resources, low design complicity and the like.

Description

technical field [0001] The invention relates to the field of digital communication channel coding, in particular to a design method of a QC-LDPC decoder for improving node processing parallelism. Background technique [0002] For the design of the LDPC code decoder, it is theoretically possible to implement an LDPC code decoder with a fully parallel structure based on all nodes and edges in the bipartite graph. However, with the increase of the code length, the excessive wiring complexity and huge The resource requirements will make it difficult to implement a decoder with a fully parallel structure. Although the serial structure can reduce the consumption of hardware resources, the lower decoding throughput usually cannot meet the needs of practical applications. In 2001, Kou et al. (Y.Kou, S.Lin, and M.P.C.Fossorier, "Low-density parity-check codes based on finite geometries: A rediscovery and new results," IEEE Trans.Inform.Theory, 2001, 47(7 ):2711–2736) proposed quasi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 谢天娇袁瑞佳靳凡杨新权李立
Owner XIAN INSTITUE OF SPACE RADIO TECH
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