High-speed data caching structure and method

Abstract

The invention discloses a high-speed data caching structure and method. The high-speed data caching structure comprises a front-end receiving data caching unit, a middle-end large-capacity data caching unit, a rear-end sending data caching unit and a caching data control unit, wherein the front-end receiving data caching unit comprises a double-port Block RAM, an A port of the BRAM of the front-end receiving data caching unit is used for writing data to be cached, and a B port of the BRAM of the front-end receiving data caching unit is used for reading the data to be cached to the middle-end large-capacity data caching unit; the middle-end large-capacity data cache unit comprises a high-speed cache chip DDR3, time-sharing ping-pong operation is adopted for executing write-in and read-out,and it is guaranteed that the write priority is higher than that of read in the process; the rear-end sending data cache unit comprises a dual-port Block RAM, an A port of the BRAM of the rear-end sending data cache unit is used for writing data read by DDR, and a B port of the BRAM of the rear-end sending data cache unit is used for reading data to a next operation end; and the cache control unitis used for controlling the execution processes of the three units. According to the method, the program execution efficiency can be improved and the bit error rate can be reduced in a system with high capacity and relatively high real-time requirement.

Description

technical field [0001] The invention relates to a high-speed data cache structure and method, and belongs to the technical field of integrated circuits and microelectronics. Background technique [0002] With the rapid development of modern information technology, the cache of large-capacity data is very important in the acquisition and storage system. Common high-speed circuit board cache units are often FIFO, BRAM, DDR3 SDRAM, etc. Asynchronous FIFO and dual-port BRAM have independent read and write functions and can be widely used in cross-clock domain systems. Compared with the asynchronous FIFO, the dual-port BRAM has a larger buffer capacity, can support the read and write operations of two clocks of different sizes, and the operation on the address is more direct. However, the data cache of the ultra-large-capacity acquisition system, such as a high-speed camera, cannot meet the demand only by relying on BRAM. [0003] DDR SDRAM cache capacity is GB level, DDR3 spee...

AI Technical Summary

Problems solved by technology

However, the circuit signal of DDR is complex, which is not conducive to the control of engineers. It is necessary to develop a complex control module for operation, which increases the difficulty and time cost of development.

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