Divider and division operation method

Abstract

The invention discloses a divider and a divider operation method, and belongs to the technical field of the digital signal processing circuit. The divider adopts a cardinal number N algorithm, wherein N is 2i, i is a positive integer greater than or equal to 3, and the quotient of an initial dividend and an initial divisor is greater than or equal to -N or less than or equal to N. The divider comprises a sign bit determining unit (1), a divisor multiple calculation unit (2) and an iterative computation unit (3), wherein the sign bit determining unit (1) is used for judging the sign bit of a quotient result of the initial dividend and the initial divisor; the divisor multiple calculation unit (2) is used for calculating the P times of a numerical value bit of a non-zero initial divisor to obtain a Pth numerical value multiple value, wherein P takes an integral value successively in an interval 1-N so as to obtain N divisor multiple values; and the iterative computation unit (3) is used for carrying out K-time iterative computation on the numerical value bit of the initial dividend and N divisor multiple values to obtain an initial quotient value result. During the iterative computation of the divider, the bit of the quotient generated each time can be flexibly selected, and excessive hardware areas are not occupied while a quick operation is carried out.

Description

technical field [0001] The invention relates to the technical field of digital signal processing circuits, in particular to a divider and a division operation method. Background technique [0002] With the rapid development of modern information processing technology, the divider, as an important computing unit of the microprocessor, has been widely used in the design of electronic circuits. The operation speed, performance, and power consumption of the divider will affect the performance of the entire microprocessor, so improving the performance of the divider is a key factor for improving the performance of the entire microprocessor. [0003] There are many ways to implement the hardware of the divider: 1. Using the array divider, the entire division operation can be done in one clock cycle, but the hardware area is large and the logic delay is long; 2. Realize with a multiplier, first by calculating the divisor The reciprocal of , and then multiplied by the dividend, thi...

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Problems solved by technology

[0004] The present invention aims at the multi-period divider existing in the prior art. Each iterative calculation of the cyclic subtraction multi-cycle divider only generates a quotient number. For the technical problem of being unable to achieve an effective compromise between hardware area and operation speed, a divider and a division operation method are provided, which can flexibly select different N values ​​according to the requirements of hardware area and operation speed in practical applications. The number of digits of the quotient generated by iterative calculation, and at least three quotient digits are generated in each iterative calculation, which shortens the calculation time of division

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