Field programmable gata array (FPGA)-based metric floating-point multiplier design

Abstract

The invention discloses a field programmable gata array (FPGA)-based metric floating-point multiplier design. The design adopts advanced and quick algorithms such as densely-packed decimal (DPD) coding, novel binary-coded decimal (BCD) coding, signed-digit radix-5, decimal 32:2 carry-save adder (CSA) and the like, is realized by programming through a Verilog hardware description language and can perform multiplication of 64-digit decimal floating-point numbers in accordance with the Institute of Electrical and Electronic Engineers (IEEE) 754-2008 new standard. The design effectively solves the problem of conversion accuracy existing in binary / decimal operation on the conventional hardware platform and the time problem of the realization of decimal floating-point multiplication by using software, consumes a small number of hardware resources and has high operation speed and a simple structure; moreover, according to the performance and characteristic of the FPGA, a system can be developed repeatedly, and a decimal floating-point unit which is accordant with the IEEE 754-2008 standard specification can be further developed and designed. The design is mainly applied to industries such as bank finance, image processing, medical treatment and the like.

Description

Technical field [0001] The present invention relates to a kind of FPGA-based decimal floating-point multiplier design, which has adopted DPD (Densely-packeddecimal) coding, novel BCD coding, Signed-Digit radix-5 and Decimal 32: 2CSA and other advanced and fast algorithms, using Verilog HDL hardware description language programming implementation, capable of multiplication of 64-bit decimal floating-point numbers conforming to the new IEEE 754-2008 standard on the FPGA development platform, which is mainly used in banking, financial, image processing, and medical industries. Background technique [0002] Currently, the IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754-1985) is the most widely used standard for floating-point arithmetic and is used by many CPUs and floating-point arithmetic units. However, the launch of the new standard IEEE 754-2008 in August 2008 revised the two standards IEEE 754-1985 and IEEE 854-1987, and defined the representation specificatio...

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Problems solved by technology

[0003] In order to overcome the precision problem of binary / decimal conversion on the existing hardware platform and the time problem of software realizing the decimal multiplication operation, and in order to adapt to people's life usage, the present invention designs a kind of decimal floating-point number multiplier based on FPGA, the The multiplier not only solves the precision problem of binary / decimal conversion on the hardware platform and the time problem of software implementation of decimal floating-point multiplication, but also improves the application range of decimal floating-point multiplication

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