30 results about "Verilog hardware description language" patented technology

The invention relates to a multifunctional data acquisition module based on a compact peripheral component interconnect (CPCI) bus. The multifunctional data acquisition module comprises a hardware module and a field-programmable gate array (FPGA) program. The hardware module comprises an impedance control circuit board, an electronic component, a small computer system interface (SCSI100) signal connection socket, a standard CPCI bus connector, and a standard 3UEurocard front panel. The impedance control circuit board and the electronic component are the core functional carriers of the invention and are divided into eight functional units such as an analogue-digital (AD) conversion module, a digital-analogue (DA) conversion unit, a timer unit, a counter unit, a universal input-output (IO) unit and an auxiliary circuit unit. The FPGA program comprises an AD conversion module, a DA conversion module, a timer module, a counter module and a universal IO module and is programmed and developed by Verilog hardware description language (HDL). The multifunctional data acquisition module has steady performance, high reliability, high bus signal driving capability, far transmission distance, simple structure, powerful function, high cost performance, is convenient to use, and can perform long-term and continuous mass data transmission.

The invention relates to a compact peripheral components interconnect (CPCI)-bus-based 1553B protocol data communication and serial loading module, which comprises a hardware module and a field programmable gate array (FPGA) program. The hardware module comprises an impedance control circuit board, a signal connection socket, a standard CPCI bus connector and a standard 3UEurocard board card front panel, wherein the impedance control circuit board is the core of the module, and is divided into an FPGA unit, a CPCI bus unit, an isolating transformer unit, a logic level translation unit, a 1553B bus protocol chip unit, a serial loading unit and an auxiliary circuit unit. The FPGA program comprises a 1553B bus communication bus controller (BC) module, a remote terminal (RT) module, a monitor terminal (MT) module, and a serial loading module, and is developed by Verilog hardware description language (HDL) programming. The module has stable performance and high reliability, can perform 1553B communication for long and can be randomly set as a BC, an RT or an MT in the 1553B communication; an RT address of external equipment suspended under a 1553B bus together with the module can be serially loaded and flexibly set; the data transmission of a CPCI bus has a direct memory access (DMA) function, the actual transmission rate of the bus is 1MB/s and continuous transmission can be realized without frame loss.

The invention discloses a flexibility motion control IP (Intellectual Property) core and an implementation method thereof, belonging to the field of motion control. The IP core comprises a acceleration/deceleration module, an interpolation module, a pulse counting module, a pulse generation module, a bus controller and an RAM (Random Access Memory) interface module. The flexibility motion control IP core and the implementation method thereof aim to solve the problems that high speed and high precision cannot be achieved due to incapability of further reducing a control period since a motion control algorithm has a long running period in a general MCU (Micro Controller Unit) or DSP (Digital Signal Processor). The IP core has the characteristics of short control period and high output pulse precision, non-symmetrical linear acceleration and deceleration can be achieved, non-symmetrical S-shaped curve acceleration and deceleration can be achieved, two-axis or three-axis linear interpolation with the linear or the S-shaped curve acceleration and deceleration can be achieved, and two-axis arc interpolation at an uniform speed also can be achieved. Through the adoption of the IP core, motion control relevant algorithm is realized in a Verilog hardware description language soft core mode, the motion control relevant algorithm can be implemented in an FPGA (Field Programmable Gate Array), can be implemented in an ASIC (Application Specific Integrated Circuit) mode, and can be integrated into SoC (System On Chip), the typical working frequency is 100MHz, and feasibility is provided for building a flexibility motion control system.

Provided is a Flight Gear general three-dimensional scene data displaying method based on a field programmable gate array (FPGA). The method includes that an FPGA chip is adopted, coding of Verilog hardware description language (HDL) language is conducted on the FPGA chip, and a data transmission protocol 1 is self-defined so as to enable the FPGA chip to finish receiving of serial data of specific frame format and with the baud rate of 115200 bps, analysis of data of a self-definition communication protocol 1 is finished in the FPGA, and the data is processed through corresponding algorithms. Then, the processed data is coded and packaged through another self-definition communication protocol 2 and transmitted to a Simulink project operated on a personal computer (PC) with the baud rate as 115200 bps, a series of data processing is conducted in the Simulink. Finally, corresponding gesture data is transmitted to Flight Gear software through a user datagram protocol (UDP) network transmission module to be displayed in real time in a three-dimensional (3D) mode. The Flight Gear general three-dimensional scene data displaying method has the advantage that design and simulation of an aerospace vehicle controller, simulation of an unmanned aerial vehicle controller, simulation of guided missile control, simulation of vehicle and ship controllers and 3D visual reproduction of actual aircraft test flight data and the like can be well achieved, and a use range is wide.

The invention relates to a simulation test method of integrated circuits, which comprises the following steps of: reading in a netlist of the integrated circuits; generating corresponding list files according to data of a register, a latch, an RAM and an ROM; generating a field data preservation task and a field data recovery task according to a verilog hardware description language by the list files; transferring the field data preservation task at different simulation time points to preserve simulation field data at different appointed simulation time points; generating a plurality of mutually independent simulation threads, wherein every simulation thread starts simulation software; transferring the field data recovery task for initializing the integrated circuit which is in simulation correspondence with each simulation software into the field data preserved at different simulation time points, and starting up all the simulation threads for simulation verification. The invention greatly shortens the simulation time and improves the simulation efficiency.

The invention relates to a method for testing the fault of a multiposition memorizer inlaid in FPGA. The method comprises the following six steps of: firstly, increasing the quantity of test patterns through the formula: two multiplied by (one plus log2n) by the March C-algorithm; secondly, introducing the test patterns, the quantity of which is expressed by the formula: two multiplied by (one plus log2n) into six March units of the March C-algorithm so as to obtain the March C-algorithm for testing the memorizer based on memory cells and has the bit wide of n bit; thirdly, establishing a BIST structure in FPGA by utilizing the Verilog hardware description language; fourthly, using a control unit to control the test patterns of the tested memorizer, the state of a state controller as well as the start and stop of an internal response analyzer which are input under different states at the BIST platform, and generating the sequence of March element test patterns needed for different fault models of the memorizer by a test pattern generator; fifthly, testing the memorizer according to the generated test patterns; and sixthly, observing test wave forms, and determining the fault type of the memorizer. The method achieves simplicity and easiness for implementation, and has considerably broad application prospect in the field of testing the multiposition memorizer inlaid in FPGA.

The invention discloses an on screen display (OSD) control display method and a device based on an advanced extensible interface (AXI) bus protocol. After OSD data is selected through an OSD data channel, flexible modification and display on an OSD map layer can be achieved by utilizing of read-write cache first input, first output (FIFO) and an advanced extensible interface (AXI) bus arbitration module, wherein video memory is shared by the OSD data, and at the same time, a path of video interfaces is arranged on the exterior so as to achieve the picture-in-picture effect. A bilinearity Scaler zoom module is used for carrying out zoom process on an OSD image with random proportions, and at last an OSD and video overlap module is utilized to achieve abundant and diversified display modes of the OSD. According to the OSD control display method and the device based on an AXI bus protocol, the design of very large scale integration (VLSI) is achieved, intensive study is carried out on key points in the VLSI, and code compiling and the function of the code compiling of a Verilog-hardware description language (HDL) are achieved on the basis of the intensive study on the key points in the VLSI.

The invention relates to a field programmable gate array-based (FPGA-based) realization method for converting a liquid crystal display (LCD) signal to a video graphics array (VGA) signal, which belongs to the technical field of the FPGA design, and a system is mainly established by an FPGA module, a synchronous dynamic random access memory (SDRAM) module and a register-packs network module. The FPGA module is used as a core of a conversion system, consists of a clock management module, a resetting module, an LCD signal receiving module, a writing first-in first-out (FIFO) module, an SDRAM controller module, a reading FIFO module, an FIFO controller module and a VGA display module and is realized through a Verilog hardware description language (HDL) code; the SDRAM module is a cache for processing the data of the FPGA module, and a controller of the SDRAM module is realized inside the FPGA module; and the exclusion network module is formed by register packs and used for converting a digital signal to an analog signal. The FPGA-based realization method has the advantages of low cost, short development period, low development risk, convenience in modification design and good confidentiality.

The invention relates to a method capable of achieving UID-LED multistate control and belongs to the technical field of server design and application. The method comprises the following steps that (1)peripheral circuit design is completed; (2) a UID-LED multistate controlled module is achieved through the Verilog hardware description language; (3) a mirror image document is downloaded into a CPLD/FPGA chip of a server to achieve UID-LED multistate control; (4) key shake removing module design and key detection are conducted on a UID key by a CPLD in real time; (5) IPMI signals input by a BMCare subjected to synchronous module design and signal detection by the CPLD in real time; and (6) the signals coming from the UID key and the BMC are judged and selected. The UID signals can be preprocessed, judged, selected and controlled on the basis of CPLD-FPGA, when UID-LED effective indication signals are detected, the signal source can be judged in real time, finally, UID-LED adopts different indication modes, and then UID-LED lightening modes are effectively distinguished.

The invention provides a low voltage differential signaling (LVDS) interface integrated circuit realizing method based on the error diffusion algorithm. The method comprises the steps of educing the error diffusion algorithm to each path of RGB (red, green and blue) image data before input of LVDS, and reducing image quality reduction due to direct elimination of low-position signals. Line storage used at time of the error diffusion algorithm is designed by utilization of first in first out (FIFO), and a one-in four-out random-access memory (RAM) is set up at time of coding the LVDS interface, and therefore the condition that four RAMs (one in one out) are needed in the prior art is avoided. The LVDS interface integrated circuit realizing method finishes the very large scale integrated circuit (VLSI) design for a raised method, and conducts deep research on key points of the VLSI, and finishes code writing of Verilog-hardware description language (HDL) and function achievement.

The invention discloses a version displaying method based on a CPLD_FPGA (Complex Programmable Logic Device_Field Programmable Gate Array), and relates to the technical field of the server CPLD/FPGA.Design is carried out through a Verilog hardware description language, instantiation is carried out on a code top layer, and an LED (Light Emitting Diode) number parameter and stage version input information are given according to practical requirements; an LED control signal output by the CPLD/FPGA is connected to the LED to control the LED to be turned on and off; specifically, through an FSM (Finite State Machine), the LED is designed to carry out the time sharing display of stage version information; the LED number declares an input/ output port through a parameterization way, codes do notneed to be revised when LED number requirements are different in different designs, but an application can be directly instantiated. By use of the method, on a premise that no additional LEDs and CPLD/FPGA chips are added, stage information and version information can be simultaneously displayed, and hardware cost is lowered; and meanwhile, a transplantation problem brought by different LED numbers is solved, and code transplantation ability is increased.

The invention discloses a high speed video data acquisition display system and a display method. The high speed video data acquisition display system comprises an FPGA controller and an alarming module connected with the FPGA controller, and the FPGA controller is connected with an OV7607camera by a camera configuration module and an SCCB bus. The OV7607 camera is used to transmit the acquired data information to the FPGA controller, which is connected with a projector/display by a VGA interface, and is connected with a CPU by a JTAG interface. The front segment camera (OV7670) is used for data acquisition, and is used to store the data in the internal RAM of the FPGA. The FPGA is used to realize fast reading/writing and transceiving control, and under control of a Nios II, the CPU is used to control the acquired data on the VGA display screen. A verilog hardware description language is used to initialize the SCCB bus, and the data acquired by the camera is stored in the internal RAM of the FPGA, and under excitation of clock pulses, the real-time data information is stored constantly, and high matching compatibility is achieved, and then a high efficiency and high speed data acquisition function is realized.

The invention relates to a file status acquisition method using the Verilog hardware description language. It is composed of the following steps. Setup a file register group composed of more than one register, and stores the file data in the file register group when handling the files. Determine whether the data in the register group is the original value of the corresponding data stored register. If it is, the register is empty. Otherwise the register is not empty, and the file status is determined according to the register status of the mentioned file register group. The invention implements the file status determination based on the Verilog language without involving the other languages. By this means, the file dynamically read-write exchanging can be implemented in the disk.

The invention discloses an adaptive real-time image background removing method and system, and the system comprises a data storage module which is used for storing image data or a background model; an image reading and writing module which is used for receiving image data and storing the received image data in the data storage module; and a background removing module which reads the image data and the corresponding background module from the data storage module, and carries out the background discrimination of the image data according to the background model. The background removing module generates a mask code corresponding to the image data according to a discrimination result, and the image data with the background being removed, and enables the image data with the background being removed and/or the mask code to be stored in the data storage module. The system designs a hardware circuit through employing a Verilog hardware description language, is implemented on an FPGA, and is high in transplantability. Moreover, the background removing module can serve as an IP core to be used in other systems, thereby meeting more demands.

The invention provides a clock path information generation method and device, electronic equipment and a medium. Through a preset clock path information generation tool, the problem of rapid development of clock network circuits for different large-scale SoC chips is solved. Specifically, clock network information is imported into a clock path information generation tool (an implementation carrier is a script language, such as a Perl language), and clock path code information (such as a Verilog hardware description language) and clock path block diagram information are automatically generated by utilizing the clock path information generation tool, so that an efficient and error-free SoC chip clock network is quickly realized. The SoC chip development time can be greatly shortened, and the design efficiency is improved.