30 results about "Verilog hardware description language" patented technology

The invention discloses a flexibility motion control IP (Intellectual Property) core and an implementation method thereof, belonging to the field of motion control. The IP core comprises a acceleration / deceleration module, an interpolation module, a pulse counting module, a pulse generation module, a bus controller and an RAM (Random Access Memory) interface module. The flexibility motion control IP core and the implementation method thereof aim to solve the problems that high speed and high precision cannot be achieved due to incapability of further reducing a control period since a motion control algorithm has a long running period in a general MCU (Micro Controller Unit) or DSP (Digital Signal Processor). The IP core has the characteristics of short control period and high output pulse precision, non-symmetrical linear acceleration and deceleration can be achieved, non-symmetrical S-shaped curve acceleration and deceleration can be achieved, two-axis or three-axis linear interpolation with the linear or the S-shaped curve acceleration and deceleration can be achieved, and two-axis arc interpolation at an uniform speed also can be achieved. Through the adoption of the IP core, motion control relevant algorithm is realized in a Verilog hardware description language soft core mode, the motion control relevant algorithm can be implemented in an FPGA (Field Programmable Gate Array), can be implemented in an ASIC (Application Specific Integrated Circuit) mode, and can be integrated into SoC (System On Chip), the typical working frequency is 100MHz, and feasibility is provided for building a flexibility motion control system.

The invention provides a pure electronic speed feedback method for an asynchronous motor. The specific operation steps are as follows: first obtain the discrete-time form expression of the mathematical model of the asynchronous motor, and then obtain the reduced-order EKF speed estimation algorithm for the asynchronous motor according to the extended Kalman filter algorithm, and then Design the algorithm structure of FPGA to realize the reduced-order EKF speed estimation. Based on the algorithm structure described above, the FPGA is described in hardware language VHDL, and the state estimated values ​​iαs, iβs, Ψαr, Ψβr, ωr are sent to the parallel port and sent back to the main control DSP. The present invention greatly reduces the pressure on the real-time calculation amount of the main control DSP, leaving more storage space and calculation space for speed and current control; and the EKF speed estimation algorithm implemented in parallel by FPGA can be implemented within 1 μs level Complete, so that the speed estimation algorithm can choose a smaller sampling period, so the speed estimation accuracy is greatly improved.

The invention provides a clock path information generation method and device, electronic equipment and a medium. Through a preset clock path information generation tool, the problem of rapid development of clock network circuits for different large-scale SoC chips is solved. Specifically, clock network information is imported into a clock path information generation tool (an implementation carrier is a script language, such as a Perl language), and clock path code information (such as a Verilog hardware description language) and clock path block diagram information are automatically generated by utilizing the clock path information generation tool, so that an efficient and error-free SoC chip clock network is quickly realized. The SoC chip development time can be greatly shortened, and the design efficiency is improved.

The invention relates to a method for testing the fault of a multiposition memorizer inlaid in FPGA. The method comprises the following six steps of: firstly, increasing the quantity of test patterns through the formula: two multiplied by (one plus log2n) by the March C-algorithm; secondly, introducing the test patterns, the quantity of which is expressed by the formula: two multiplied by (one plus log2n) into six March units of the March C-algorithm so as to obtain the March C-algorithm for testing the memorizer based on memory cells and has the bit wide of n bit; thirdly, establishing a BIST structure in FPGA by utilizing the Verilog hardware description language; fourthly, using a control unit to control the test patterns of the tested memorizer, the state of a state controller as well as the start and stop of an internal response analyzer which are input under different states at the BIST platform, and generating the sequence of March element test patterns needed for different fault models of the memorizer by a test pattern generator; fifthly, testing the memorizer according to the generated test patterns; and sixthly, observing test wave forms, and determining the fault type of the memorizer. The method achieves simplicity and easiness for implementation, and has considerably broad application prospect in the field of testing the multiposition memorizer inlaid in FPGA.

The invention discloses a robot ultrasonic sensor obstacle detection method and system, which belong to the field of robots and embedded systems. The technical problem to be solved in the invention is how to make the robot avoid obstacles more accurately. The technical solution adopted is: The FPGA processor platform of the robot performs real-time calculation and processing of data, and the Verilog hardware description language is used in the FPGA for digital logic design; the details are as follows: ultrasonic sensor variable field of view measurement and ultrasonic sensor rotation measurement; distance measurement after t time; Record the real-time distance value after time; calculate the optimal estimate of the current distance value according to the Kalman filter algorithm; iteratively calculate the optimal estimate of the distance; update the grid map and make decisions to avoid obstacles; the FPGA processor platform controls the robot navigation The module provides decision-making basis to realize precise obstacle avoidance of the robot.

The invention relates to a compact peripheral components interconnect (CPCI)-bus-based 1553B protocol data communication and serial loading module, which comprises a hardware module and a field programmable gate array (FPGA) program. The hardware module comprises an impedance control circuit board, a signal connection socket, a standard CPCI bus connector and a standard 3UEurocard board card front panel, wherein the impedance control circuit board is the core of the module, and is divided into an FPGA unit, a CPCI bus unit, an isolating transformer unit, a logic level translation unit, a 1553B bus protocol chip unit, a serial loading unit and an auxiliary circuit unit. The FPGA program comprises a 1553B bus communication bus controller (BC) module, a remote terminal (RT) module, a monitor terminal (MT) module, and a serial loading module, and is developed by Verilog hardware description language (HDL) programming. The module has stable performance and high reliability, can perform 1553B communication for long and can be randomly set as a BC, an RT or an MT in the 1553B communication; an RT address of external equipment suspended under a 1553B bus together with the module can be serially loaded and flexibly set; the data transmission of a CPCI bus has a direct memory access (DMA) function, the actual transmission rate of the bus is 1MB / s and continuous transmission can be realized without frame loss.

The invention relates to a simulation test method of integrated circuits, which comprises the following steps of: reading in a netlist of the integrated circuits; generating corresponding list files according to data of a register, a latch, an RAM and an ROM; generating a field data preservation task and a field data recovery task according to a verilog hardware description language by the list files; transferring the field data preservation task at different simulation time points to preserve simulation field data at different appointed simulation time points; generating a plurality of mutually independent simulation threads, wherein every simulation thread starts simulation software; transferring the field data recovery task for initializing the integrated circuit which is in simulationcorrespondence with each simulation software into the field data preserved at different simulation time points, and starting up all the simulation threads for simulation verification. The invention greatly shortens the simulation time and improves the simulation efficiency.

The invention relates to a multifunctional data acquisition module based on a compact peripheral component interconnect (CPCI) bus. The multifunctional data acquisition module comprises a hardware module and a field-programmable gate array (FPGA) program. The hardware module comprises an impedance control circuit board, an electronic component, a small computer system interface (SCSI100) signal connection socket, a standard CPCI bus connector, and a standard 3UEurocard front panel. The impedance control circuit board and the electronic component are the core functional carriers of the invention and are divided into eight functional units such as an analogue-digital (AD) conversion module, a digital-analogue (DA) conversion unit, a timer unit, a counter unit, a universal input-output (IO) unit and an auxiliary circuit unit. The FPGA program comprises an AD conversion module, a DA conversion module, a timer module, a counter module and a universal IO module and is programmed and developed by Verilog hardware description language (HDL). The multifunctional data acquisition module has steady performance, high reliability, high bus signal driving capability, far transmission distance, simple structure, powerful function, high cost performance, is convenient to use, and can perform long-term and continuous mass data transmission.

The invention relates to a method capable of achieving UID-LED multistate control and belongs to the technical field of server design and application. The method comprises the following steps that (1)peripheral circuit design is completed; (2) a UID-LED multistate controlled module is achieved through the Verilog hardware description language; (3) a mirror image document is downloaded into a CPLD / FPGA chip of a server to achieve UID-LED multistate control; (4) key shake removing module design and key detection are conducted on a UID key by a CPLD in real time; (5) IPMI signals input by a BMCare subjected to synchronous module design and signal detection by the CPLD in real time; and (6) the signals coming from the UID key and the BMC are judged and selected. The UID signals can be preprocessed, judged, selected and controlled on the basis of CPLD-FPGA, when UID-LED effective indication signals are detected, the signal source can be judged in real time, finally, UID-LED adopts different indication modes, and then UID-LED lightening modes are effectively distinguished.