Method for acquiring file status by using Verilog hardware description language

Abstract

The invention relates to a file status acquisition method using the Verilog hardware description language. It is composed of the following steps. Setup a file register group composed of more than one register, and stores the file data in the file register group when handling the files. Determine whether the data in the register group is the original value of the corresponding data stored register. If it is, the register is empty. Otherwise the register is not empty, and the file status is determined according to the register status of the mentioned file register group. The invention implements the file status determination based on the Verilog language without involving the other languages. By this means, the file dynamically read-write exchanging can be implemented in the disk.

Description

technical field [0001] The invention relates to the technical field of electronic system simulation design, in particular to a method for obtaining file status by using Verilog hardware description language (HDL, Hardware Description Language). Background technique [0002] With the expansion and complexity of electronic systems in electronic design, designers must use hardware description languages ​​to design complex electronic systems through simulation and modeling. At present, the hardware description languages ​​mainly used in electronic design are VHDL and Verilog HDL. Among them, VerilogHDL was launched late. This language is more suitable for digital system modeling at various abstract design levels from algorithm level, register transfer level, logic level, gate level to switch level, and its syntax is flexible, easy to grasp, and functional. Comprehensive, good scalability and other characteristics, and gradually become a hardware description language widely used...

AI Technical Summary

Problems solved by technology

Although the designers and testers of this scheme do not need to be directly exposed to C language programming, how to use the Verilog file operating system task extended through the stdio function also needs to be re-learned, and how to connect with the simulation tool during simulation is also useful for different simulation tools. Different requirements, on the one hand, this brings inconvenience to the test, on the other hand, it causes poor portability of the test code,

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