Method for acquiring file status by using Verilog hardware description language

A hardware description language and file technology, applied in the direction of program control design, instruments, electrical digital data processing, etc., can solve the problems of inconvenient testing, poor test code portability, inconvenient user design and testing, etc., to achieve enhanced operation functions, Simple code writing and good code portability

CN1306398CInactive Publication Date: 2007-03-21HUAWEI TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2007-03-21
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention relates to a file status acquisition method using the Verilog hardware description language. It is composed of the following steps. Setup a file register group composed of more than one register, and stores the file data in the file register group when handling the files. Determine whether the data in the register group is the original value of the corresponding data stored register. If it is, the register is empty. Otherwise the register is not empty, and the file status is determined according to the register status of the mentioned file register group. The invention implements the file status determination based on the Verilog language without involving the other languages. By this means, the file dynamically read-write exchanging can be implemented in the disk.
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Description

technical field

[0001] The invention relates to the technical field of electronic system simulation design, in particular to a method for obtaining file status by using Verilog hardware description language (HDL, Hardware Description Language). Background technique

[0002] With the expansion and complexity of electronic systems in electronic design, designers must use hardware description languages ​​to design complex electronic systems through simulation and modeling. At present, the hardware description languages ​​mainly used in electronic design are VHDL and Verilog HDL. Among them, VerilogHDL was launched late. This language is more suitable for digital system modeling at various abstract design levels from algorithm level, register transfer level, logic level, gate level to switch level, and its syntax is flexible, easy to grasp, and functional. Comprehensive, good scalability and other characteristics, and gradually become a hardware description language widely used...

Examples

Embodiment Construction

[0025] In the solution of the present invention, when creating a file register group for storing file data, all registers in the file register group are specified as a certain original value. Use the system task $readmemb or $readmemh provided in the Verilog language standard to read the file. When the file data is read into the register of the file register group, the content of the file data will overwrite the original value of the register where it is located. In this way, it is possible to determine whether the register is empty by comparing whether the data content in the register is consistent with the original value of the register, and then know the file status information corresponding to the file register group, such as: whether the file is empty, the data in the file number, the end point of the file, and whether the file has been read.

[0026] Below, the preferred embodiment of the present invention is described in detail by taking the read operation process of t...