Method for testing fault of multiposition memorizer inlaid in FPGA

Abstract

The invention relates to a method for testing the fault of a multiposition memorizer inlaid in FPGA. The method comprises the following six steps of: firstly, increasing the quantity of test patterns through the formula: two multiplied by (one plus log2n) by the March C-algorithm; secondly, introducing the test patterns, the quantity of which is expressed by the formula: two multiplied by (one plus log2n) into six March units of the March C-algorithm so as to obtain the March C-algorithm for testing the memorizer based on memory cells and has the bit wide of n bit; thirdly, establishing a BIST structure in FPGA by utilizing the Verilog hardware description language; fourthly, using a control unit to control the test patterns of the tested memorizer, the state of a state controller as well as the start and stop of an internal response analyzer which are input under different states at the BIST platform, and generating the sequence of March element test patterns needed for different fault models of the memorizer by a test pattern generator; fifthly, testing the memorizer according to the generated test patterns; and sixthly, observing test wave forms, and determining the fault type of the memorizer. The method achieves simplicity and easiness for implementation, and has considerably broad application prospect in the field of testing the multiposition memorizer inlaid in FPGA.

Description

technical field [0001] The invention relates to a memory test method, in particular to a test method for faults of embedded multi-bit memory inside FPGA, and belongs to the field programmable gate array test technology field of FPGA. Background technique [0002] Field Programmable Gate Array (hereinafter referred to as FPGA) is a new type of programmable logic device that appeared in the mid-1980s. Its main feature is that it is completely configured and programmed by the user through software to complete a specific function and can be repeatedly erased. . When modifying and upgrading, there is no need to change the PCB circuit board additionally, just modify and update the program on the computer, so that the hardware design work becomes software development work, which shortens the cycle of system design, improves the flexibility of implementation and reduces the cost of R&D. Therefore, it has won the favor of the majority of hardware engineers. [0003] With the increa...

AI Technical Summary

Problems solved by technology

[0021] If the above-mentioned March C-algorithm is directly extended into a cell-oriented memory test algorithm, coupling faults between storage cells can be detected, but coupling faults within storage cells cannot be detected

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