On-board test method for memory

A test method and memory technology, applied in static memory, instruments, etc., can solve problems such as high time consumption, and achieve the effects of high timeliness, good fault coverage, good fault coverage and timeliness

Inactive Publication Date: 2010-07-07
中国航空工业第一集团公司第六三一研究所
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  • Abstract
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Problems solved by technology

[0003] The purpose of the present invention is to provide a memory on-board test method, which has high timeliness and solves the technical problem of high time consumption caused by the existing memory chip test

Method used

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Embodiment Construction

[0025] see figure 1 , the test method of the present invention is mainly divided into three-step tests in order: the first step is a code input method test, the second step 01 step method is used to test data lines and address lines, and the third step is March algorithm test. The first step is basically to test the data line and address line. If it is not a memory fault, the fault pattern can provide help in locating the faulty chip; the second step is to locate the specific data / address line, and you can also test part of the memory. unit; the third step memory test.

[0026] 1. Test with fancy code data input method

[0027] For the test input data, according to the distance effect (the Hamming distance of the two test vectors - the greater the number of corresponding bits of the two test vectors, the more different faults they can detect), select the flower with the largest difference between the two groups The code data is used as data input, and the data bus is set to ...

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Abstract

The invention relates to a test method for a memory, comprising the following tests in sequence: control line test, Chinese numerals data input method test, 01 stepping technique test and March algorithm test. The method of the invention is supposed to have high timeliness at first; then the method is supposed to have high fault-coverage rate on line fault; in addition, the method is supposed to take into account detection of self fault of a memory chip; moreover the method of the invention covers self fault of the memory chip and circuit board line fault, strikes a good balance between test requirements and test consumption, thus enjoying good fault-coverage rate and timeliness and being applicable to on-board test of various memories.

Description

technical field [0001] The invention relates to a memory testing method, in particular to a memory on-board testing method. Background technique [0002] At present, for the test of memory chips, some mature algorithms have been widely used in the design of test methods, such as March, Walk, Gallop, Damier, Movi and other algorithms. However, because the above algorithms traverse the entire address space based on a certain order, with the sufficiency of the test requirements and the continuous increase of the memory space, the test steps will increase exponentially, and the time and resources required for the test will also increase. doubled increase. However, for on-board testing, there are usually strict requirements on the testing time and efficiency of a single module after the module is produced off-line, and the high time consumption of the memory chip testing algorithm obviously cannot meet the actual testing needs. In addition, for the test of the on-board memory, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00
Inventor 崔强彭刚锋叶关山
Owner 中国航空工业第一集团公司第六三一研究所
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