7results about How to "Shorten the control cycle" patented technology

This invention belongs to the field of digital control systems for power electronic devices. It provides a high-speed communication system and method for multiple units of CHB frequency converter based on FPGA ping-pong buffer. By building an efficient parallel processing architecture at the FPGA hardware level, it realizes zero-wait instruction issuance and instantaneous status acquisition between the controller and dozens of distributed power units, compressing the system communication and processing time from milliseconds to hundreds of microseconds, achieving the technical effect of CHB frequency converters achieving extremely short control cycles and high dynamic performance.

The invention provides an industrial control system based on a fused memory architecture and a redundant data communication method, and is applied to the technical field of industrial control. The industrial control system comprises a main controller and a standby controller, and accesses the external memory through a high-speed interface. According to the redundant data communication method, the redundant data are classified and synchronized to the external memory to ensure that the standby controller acquires the data in real time, so that the industrial control system can quickly synchronize necessary redundant data between the main controller and the standby controller, thereby realizing real-time and reliable synchronization of the redundant data, effectively shortening the control period and improving the control efficiency. And the overall performance of the industrial controller is improved.

The present invention relates to a robot system and a robot. The robot system of the present invention comprises: a sensor (60) for acquiring data for detecting at least the position of a moving object (O); a robot (10) equipped with a tool (30) and performing a predetermined operation on the object (O) using the tool (30); and a control unit for controlling a tool moving device (40), the tool (30), or an arm member at the front end side of an arm (12) of the robot (10) with a tool control cycle shorter than the control cycle of the robot (10), wherein the tool moving device (40) moves the tool (30) relative to the robot (10).

The utility model provides an intelligent composite air cooling device which comprises an outer shell, a draught fan, a dry type air cooling unit, a water collecting device, a spraying pipe, an evaporative cooling unit and a circulating water tank are sequentially arranged in the outer shell from top to bottom, and the dry type air cooling unit is communicated with the evaporative cooling unit. A working medium can be led out after sequentially passing through the dry-type air cooling unit and the evaporative cooling unit, and a medium leading-out pipe communicated with the evaporative cooling unit is mounted on the outer shell; the fresh air channel is arranged between the dry-type air cooling unit and the water collecting device, so that outside air can penetrate through the electric shutter to enter the fresh air channel, newly introduced cold air and wet and hot air penetrating through the water collecting device are mixed to achieve the cooling purpose, the original logarithmic temperature difference of an air cooling section is improved, and the cooling efficiency is improved. Meanwhile, the total heat load of the evaporation section can be reduced, the water consumption of the evaporation section is reduced, and the total amount of water vapor entering the air cooling section is reduced.

The present invention belongs to the field of digital circuit technology, and proposes a synchronous control method based on FPGA, which includes: FPGA logic determines whether the synchronization condition is met, if it is met, then the logic controls two devices to be synchronized to each send out a first synchronization indication signal, and continuously collects the synchronization indication signal sent by the other device until the first synchronization is achieved; after the first synchronization is achieved, the logic controls the two devices to be synchronized to each send out a second synchronization indication signal, and continuously collects the synchronization indication signal of the other device until the second synchronization is achieved; when the synchronization is achieved, the logic controls the two devices to control the wing movement at the same time. The present invention can execute a set of established synchronous control strategies through FPGA when the conditions for folding / unfolding the left and right wings cannot be met at the same time, thereby quickly and accurately realizing the synchronous output of the left and right wings, and significantly improving the control timeliness and product reliability.

The invention relates to the technical field of electromechanical control, in particular to a method and system for improving motor control performance based on the MPSoC technology, and the system comprises a motor body, an MPSoC chip and an upper computer. The MPSoC chip comprises a PL module and a PS module; the PL module is used as an FPGA structure, and the PS module is used as an MCU structure; the PL module and the PS module are connected through an AXI bus in the chip and carry out information interaction; the PL module is connected with the motor body, and the PS module is connected with the upper computer; according to the electric drive control system, the MPSoC chip is used as an electric drive control main body, so that the control period and the fault protection response time are reduced, and the response efficiency of the electric drive control system is improved.

The embodiment of the invention discloses a video code rate adjustment method and device, equipment and a storage medium, and the method comprises the steps: obtaining a cache utilization rate, a current video code rate, the receiving and transmitting time of each data packet, the current time and a transmission state evaluation value, and calculating a risk value based on the current video code rate and a preset upper limit code rate; periodically calculating a link cache utilization rate according to the receiving and transmitting time of each data packet, and periodically calculating an estimated frame delay time according to the current time and the receiving and transmitting time of each data packet; counting a plurality of estimated frame delay times in a preset duration range, generating a data sequence corresponding to the estimated frame delay times based on the calculation sequence, and determining a congestion state according to the link cache utilization rate, the transceiving time of each data packet and the data sequence; and determining a current adjustment strategy according to the congestion state, the transmission state evaluation value, the risk value and a preset adjustment rule, and adjusting the current video code rate based on the current adjustment strategy. The fine granularity and timeliness of congestion detection and the accuracy of code rate adjustment are improved, and the code rate control period is shortened.