A High-Speed ​​Communication System and Method for Multi-Unit CHB Frequency Converters Based on FPGA Ping-Pong Buffer

Abstract

This invention belongs to the field of digital control systems for power electronic devices. It provides a high-speed communication system and method for multiple units of CHB frequency converter based on FPGA ping-pong buffer. By building an efficient parallel processing architecture at the FPGA hardware level, it realizes zero-wait instruction issuance and instantaneous status acquisition between the controller and dozens of distributed power units, compressing the system communication and processing time from milliseconds to hundreds of microseconds, achieving the technical effect of CHB frequency converters achieving extremely short control cycles and high dynamic performance.

Description

Technical Field

[0001] This invention belongs to the field of digital control systems for power electronic devices, and specifically relates to a real-time data interaction technology between the controller and power unit of a cascaded H-bridge high-voltage frequency converter. Background Technology

[0002] Cascaded H-Bridge (CHB) high-voltage frequency converters, with their modular structure, low output voltage harmonic content, and four-quadrant operation capabilities, have become the mainstream topology in the field of medium- and high-voltage high-power motor drives. Their core feature lies in achieving the synthesis and precise control of the high-voltage side voltage by directly connecting the outputs of multiple low-voltage H-bridge power units in series. Taking a typical 13.8kV system as an example, 36 power units (12 per phase) are typically cascaded. Each unit independently receives pulse-width modulation commands from the central controller and reports its own operating status (such as faults, current, temperature, etc.) in real time.

[0003] In this distributed control architecture, high-speed and reliable data interaction between the main controller (typically a digital signal processor, DSP) and dozens of physically distributed power units is the key foundation for ensuring the system's real-time performance, stability, and reliability. Currently, the industry widely uses fiber optic communication to solve the problems of electrical isolation and interference immunity between the controller and the power units.

[0004] However, with the increase in the number of power units, communication system design faces serious challenges:

[0005] DSP interface resource bottleneck. The number of communication peripherals (such as SPI, UART, CAN) of mainstream industrial-grade DSPs is limited, making it difficult to directly support dozens of independent fiber optic channels. Even with interface expansion via FPGA, traditional serial communication methods (such as instantiating an independent UART core for each channel) consume a large amount of FPGA logic resources and input / output pins.

[0006] The system faces a real-time bottleneck. If software polling or simple serial communication is used, the DSP needs to exchange data with each unit sequentially. For a 36-unit system, assuming each communication takes 50μs, a complete bidirectional communication cycle will take as long as 3.6ms. This not only severely restricts the DSP's computational resources allocated to core control algorithms (such as SVPWM), but also forces a prolonged overall system control cycle, thus limiting dynamic response performance and causing protection delays in the event of a fault.

[0007] Software complexity and reliability bottlenecks. Managing dozens of asynchronous communication links significantly increases the complexity of the DSP software, including communication protocol parsing, timeout retransmission, and error handling. The complex software state machine also introduces uncertainty, reducing the overall system reliability.

[0008] To address these issues, existing technologies have attempted to employ high-speed serial buses (such as the FPGA-based Aurora protocol) or dedicated communication ASICs. However, the former is costly to implement on FPGAs and has complex protocols; the latter increases additional hardware costs and design complexity, reducing system flexibility.

[0009] Therefore, there is an urgent need for a multi-unit parallel communication system and method that can be efficiently implemented on resource-constrained FPGAs and can meet the requirements of CHB (Cascaded H-Bridge) frequency converters for extremely short control cycles and extremely high reliability. Summary of the Invention

[0010] To address the aforementioned technical issues, this invention provides a high-speed communication system and method for multiple units of CHB frequency converters based on FPGA ping-pong buffering. By constructing an efficient parallel processing architecture at the FPGA hardware level, it enables zero-wait instruction issuance and instantaneous status acquisition between the controller and dozens of distributed power units, compressing system communication and processing time from milliseconds to hundreds of microseconds, thereby providing core support for CHB frequency converters to achieve extremely short control cycles and high dynamic performance.

[0011] The core innovation of this invention lies in the construction of a three-layer parallel hardware acceleration architecture:

[0012] (1) Topology-oriented grouping mapping logic

[0013] For the typical three-phase N-unit cascaded structure of CHB frequency converters, all power units are divided into several logical groups (e.g., 3 groups, 12 units per group) according to their physical phase (U, V, W) within the FPGA. The data packaging, distribution, and protocol processing logic within the FPGA operates in parallel, using these groups as the basic unit. This design not only simplifies the control state machine but also ensures a high degree of matching between the internal data flow and the physical topology of the frequency converter, improving processing efficiency and logical clarity.

[0014] (2) Ping-pong buffering mechanism based on dual-port Block RAM

[0015] Two dual-port Block RAMs (RAM_A and RAM_B) are allocated within the FPGA to construct a seamless data pipeline. The core operating mode is as follows: when the DSP writes all the unit control data for the next control cycle to one RAM (e.g., RAM_A) via an external bus, the FPGA's transmit logic simultaneously reads the data for the current control cycle from the other RAM (RAM_B), encodes it, and transmits it. The two processes operate completely in parallel without blocking each other. After one cycle, a hardware handshake signal switches the "read / write" roles of the two RAMs. This mechanism completely eliminates the waiting time for communication transmission during DSP data writing, achieving complete hiding of the "data write" time at the system level.

[0016] (3) Uplink channel IO virtualization and parallel decoding technology

[0017] For the uplink channel (unit status feedback), the traditional approach of instantiating an independent UART core for each channel is abandoned. Instead, an innovative, minimalist hardware structure of "edge detection + shift register" is adopted to perform parallel sampling and decoding of multiple Manchester coded signals. Each signal requires only a small amount of logic resources to achieve bit synchronization, serial-to-parallel conversion, and protocol parsing. All unit status data obtained from decoding are stored in parallel into a centralized status register array. This array is directly mapped to the DSP's address space through a memory interface (such as XINTF), enabling the DSP to instantly obtain the status information of all units in a single burst read operation, just like accessing local memory, reducing access latency to the microsecond level.

[0018] The method described in this invention specifically includes the following steps:

[0019] Step 1: Downlink transmission process (control command issuance):

[0020] Step 1.1: The DSP uses an external parallel bus (such as EMIF) to write the duty cycle data of each power unit in the next PWM cycle into the dual-port RAM (e.g., RAM_A) of the "current write area" mapped by the FPGA address in batches.

[0021] Step 1.2: At the same time, the FPGA's hardware transmission engine reads the control data that needs to be sent to all units in the current cycle from the "current read area" dual-port RAM (e.g., RAM_B) in parallel.

[0022] Step 1.3: The FPGA performs parallel-to-serial conversion on the read data according to the packet mapping logic, and encapsulates it into fiber optic protocol frames such as Manchester encoding, and drives all downlink fiber optic channels in parallel through physical I / O.

[0023] Step 1.4: When the FPGA finishes sending data and the DSP finishes writing data for the next cycle, the hardware synchronization logic generates a switching signal to exchange the "read / write" attributes of the two RAMs (RAM_A becomes the read area and RAM_B becomes the write area), and the system enters the next cycle.

[0024] Step 2: Uplink Reception Process (Unit Status Acquisition):

[0025] Step 2.1: The FPGA's input I / O samples the Manchester-coded signals of all uplink fiber channel inputs in parallel.

[0026] Step 2.2: For each signal, a dedicated edge detection circuit restores the output synchronization clock and controls the corresponding shift register to perform serial data reception and serial-to-parallel conversion.

[0027] Step 2.3: The Manchester decoding logic extracts the original status data (such as fault flags, current values, temperature, etc.) of each power unit in parallel from the shift register and updates it to the global status register array in real time.

[0028] Step 2.4: This status register array is linearly mapped to the DSP's external memory interface (such as XINTFZone7). The DSP can obtain a complete status snapshot of all 36 cells within microseconds with only one bus read operation, without any software polling or protocol parsing.

[0029] Step 3: Exception Handling

[0030] Step 3.1: Hardware Timeout and CRC Check

[0031] Step 3.1.1: The FPGA uplink channel is equipped with an independent 32-bit timeout counter, which accumulates when there is no valid frame. When the threshold is exceeded, the "communication timeout" flag is automatically set and an interrupt can be triggered optionally.

[0032] Step 3.1.2: The FPGA automatically adds a CRC8 checksum before downlink transmission. The uplink receiver completes automatic verification. If the verification fails, the "data error" flag is immediately set.

[0033] Step 3.2: Monitoring the rate of change of state (hardware implementation):

[0034] Step 3.2.1: FPGA built-in rate of change monitoring logic. For the first... The state value of each unit The FPGA stores its previous cycle value. And calculate the change:

[0035]

[0036] Step 3.2.2: Calculate the change amount , compared with the DSP preset threshold Comparison, that is

[0037]

[0038] This comparison operation is performed in parallel across 36 channels and completed within one clock cycle. The alarm flag is integrated into the status word for the DSP to read.

[0039] Step 3.3: Fault Data Snapshot Caching:

[0040] Step 3.3.1: When the "communication timeout", "data error" or "rate of change alarm" flag of any channel is triggered, the FPGA automatically stores the raw data of the current time and the previous few cycles of that channel into a dedicated, cyclically overwritten fault snapshot RAM.

[0041] Step 3.3.2: Record the fault timestamp and channel number (do this simultaneously with Step 3.3.1).

[0042] To implement the above method, the present invention also provides a high-speed communication system for multiple units of CHB frequency converters based on FPGA ping-pong buffer, specifically including:

[0043] DSP: As the control core, it directly accesses the memory area mapped inside the FPGA through the external memory interface;

[0044] FPGA: It integrates three core modules: a status register array, a ping-pong dual-port RAM, and a packet encoding / decoding logic, which are responsible for status buffering, instruction buffering, and fiber optic protocol conversion, respectively.

[0045] Controlled units: There are 36 units, each connected to the FPGA via an independent fiber optic channel;

[0046] The DSP is connected to the FPGA via its external interface's 16-bit data bus, address bus, and control lines. Each uplink channel of the FPGA is equipped with an independent 32-bit timeout counter, and the FPGA has built-in change rate monitoring logic.

[0047] The beneficial effects of this invention are:

[0048] 1. Highly optimized resources: It adopts group mapping and parallel sampling to replace the traditional serial core, realizing high-density fiber optic communication on low-end FPGAs with limited IO resources, saving more than 70% of logic resources.

[0049] 2. The system performance is significantly improved. The ping-pong buffer mechanism based on dual-port RAM completely hides the DSP write time, and the control cycle is shortened from milliseconds to microseconds.

[0050] 3. It has good scalability and adaptability, supports dynamic grouping and parameter configuration, and can flexibly adapt to different application scales and communication needs.

[0051] 4. Significantly enhanced reliability, integrating hardware-level timeout monitoring, CRC check and fault snapshot functions to achieve fully autonomous fault diagnosis, with system real-time performance and robustness far exceeding software implementation solutions.

[0052] 5. While ensuring highly reliable communication, it provides a simple memory mapping interface for the DSP, greatly reducing system complexity and development difficulty. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the overall system architecture of the present invention.

[0055] Figure 2 This is a flowchart of the downlink data processing ping-pong buffer of the present invention.

[0056] Figure 3 This is a block diagram illustrating the principle of parallel sampling and decoding of uplink data in this invention.

[0057] Figure 4 This is a flowchart of the downlink ping-pong buffer state machine of the present invention.

[0058] Figure 5 This is a flowchart of the software interaction process of the present invention.

[0059] Figure 6 This is a schematic diagram of the dynamic reconstruction of the present invention. Detailed Implementation

[0060] The technical solution of the present invention will now be clearly and completely described with reference to specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0061] This invention proposes a distributed control communication architecture based on DSP and FPGA collaboration, such as... Figure 1 As shown, the core of the system lies in using the FPGA as a high-speed data exchange and protocol processing hub to realize full-duplex, high real-time data interaction between the main controller (DSP) and 36 controlled units.

[0062] The system architecture can be divided into two layers: hardware modules and data flow.

[0063] At the hardware module level, the DSP serves as the control core and directly accesses the memory area mapped inside the FPGA through the external memory interface (XINTF). The FPGA integrates three core modules: a status register array, a ping-pong dual-port RAM, and a group encoding and decoding logic, which are responsible for status buffering, instruction buffering, and fiber optic protocol conversion, respectively. The 36 controlled units are connected to the FPGA through independent fiber optic channels.

[0064] At the data flow level, the system implements two parallel hardware acceleration paths: an uplink path (status acquisition) and a downlink path (command issuance), namely:

[0065] Uplink path (status acquisition): The unit status is input to the FPGA in parallel via optical fiber and written to the status register in real time through group decoding logic. The DSP can directly read the status in batches through the XINTF interface to achieve microsecond-level status acquisition.

[0066] Downlink path (instruction issuance): The DSP writes control instructions in batches into the dual-port RAM of the FPGA. The FPGA encoding logic reads the instructions in parallel and sends them to each unit through optical fiber. During this process, a ping-pong buffer mechanism is used to achieve parallel writing by the DSP and sending by optical fiber without waiting.

[0067] This architecture leverages the parallel processing capabilities and programmability of FPGAs to simultaneously address three major challenges under resource-constrained conditions: multi-channel fiber optic interface adaptation, protocol conversion, and data buffering. Furthermore, it provides a transparent access method for DSPs through a standard storage interface, significantly improving the overall system performance and reliability.

[0068] like Figure 2 As shown, the ping-pong operation data interaction process between the DSP and FPGA based on dual RAM (RAM_A, RAM_B) is essentially achieved by switching the "write area / read area" roles of the two RAMs to realize parallel and continuous data processing.

[0069] The simplified steps of the DSP-FPGA dual-RAM ping-pong operation process are as follows:

[0070] Step 1: Start the process. Proceed to the judgment phase.

[0071] Step 2: Determine if both "DSP write complete" and "FPGA send complete" are met simultaneously. If yes, switch RAM roles (RAM_A and RAM_B swap "read area / write area"); if not, proceed to the next step.

[0072] Step 3: FPGA Read. Read data from the current read area RAM (e.g., RAM_B).

[0073] Step 4: FPGA processing. Data is grouped, encoded in parallel, and then transmitted.

[0074] Step 5: DSP Write. Write the next cycle's data to the current write area RAM (e.g., RAM_A).

[0075] Step 6: Loop. Return to the decision-making stage and repeat the process.

[0076] The core logic is a typical Ping-Pong Buffer mechanism—by using two RAMs alternately as a "write buffer" and a "read buffer," the DSP's write operations and the FPGA's read / encode / send operations can be executed in parallel, avoiding data processing wait times and improving overall efficiency.

[0077] like Figure 3 As shown, the FPGA utilizes a simplified "edge detection + shift register" hardware structure to process 36 uplink fiber optic signals in parallel, replacing 36 independent UART cores. This invention proposes an uplink data parallel sampling and decoding architecture for high-density fiber optic communication systems. For the status feedback signals of 36 controlled units, it abandons the traditional independent serial communication core scheme and adopts highly parallel hardware logic to achieve efficient acquisition.

[0078] The core processing flow is as follows: Manchester-encoded optical signals from each uplink fiber are converted by photoelectric conversion and then bit-synchronized by an independent edge detection module to generate a synchronization sampling enable. Each signal corresponds to a set of shift registers and a Manchester decoder, which completes the reception of serial data, serial-to-parallel conversion, and protocol decoding under the control of the synchronization enable. The 36 parallel status data generated by decoding are latched into a status register array in real time. This array is finally mapped to the address space of the main controller (DSP) through a memory interface (such as XINTF), enabling the DSP to obtain the latest status of all units at once through a single or burst read operation, just like accessing local memory.

[0079] The core innovation of this architecture lies in replacing multiple resource-intensive serial communication cores (such as UART) with a pure hardware parallel processing chain of "edge detection + shift register". It achieves synchronous, real-time decoding and status summary of 36 fiber optic signals with extremely low logic resource overhead, transforming complex multi-channel serial communication into a simple read of a memory area, greatly reducing the burden on the main processor and significantly improving the real-time performance of data acquisition.

[0080] The following describes the invention in detail using a Lattice LFXP2 FPGA and a TI F28335 DSP to control 36 units.

[0081] 1. System hardware connection

[0082] The DSP (F28335) connects to the FPGA via its external interface (XINTF) 16-bit data bus, address bus, and control lines (read / write, chip select, etc.). Of the FPGA's 146 user I / Os, approximately 80 are used for the DSP bus, and the remaining 66 I / Os are used to connect the photoelectric conversion circuits for 36 downlink transmit (TX) channels and 36 uplink receive (RX) channels. Both the TX and RX channels use Manchester encoding to simplify clock recovery for optical communication.

[0083] 2. FPGA Internal Logic Design

[0084] 2.1 Packet Mapping and Dual-Port RAM Configuration

[0085] In the FPGA, the 36 cells are divided into three groups: U, V, and W, with 12 cells in each group. Two dual-port Block RAMs (RAM_A and RAM_B) with a depth of 36 and a bit width of 16 bits are allocated. Each address stores 16 bits of duty cycle data for one cell. The DSP accesses the RAM's "write port" through a fixed address offset. The FPGA logic generates a read address based on the group number (high 2 bits) and the sequence number within the group (low 4 bits), and retrieves data in parallel from the other port.

[0086] 2.2 Parallel Processing of Downlink Transmission

[0087] An internal transmit state machine is generated within the FPGA, with a clock frequency N times (e.g., 16 times) of the Manchester code bit rate. Within each bit cycle, the state machine reads all 36 data bits in parallel from the currently active RAM (e.g., RAM_B), then combines this with grouping information and cyclically outputs the current bit of each signal through a multiplexer. Manchester encoding is performed in real-time during output. This process is entirely implemented in hardware logic, asynchronously and in parallel with the DSP.

[0088] 2.3 Uplink Receive Parallel Sampling and Decoding

[0089] For each RX signal, the design includes the following modules:

[0090] (1) Edge detector. It detects the rising and falling edges of the digital signal after photoelectric conversion and outputs a pulse signal synchronized with the Manchester symbol period and a level signal representing the symbol value (0 or 1).

[0091] (2) Bit synchronization and shift register. The symbol value is shifted into a shift register with a bit width of 10 using the edge detection pulse as the sampling enable (assuming that a frame of data is 10 bits).

[0092] (3) Frame decoder. When the shift register is full, Manchester decoding is performed on the registered contents to extract 8 bits of valid status data and store them in the corresponding status register.

[0093] The 36 status registers are continuously mapped to an address space inside the FPGA, which corresponds exactly to the Zone7 region of the DSP XINTF through the FPGA's address decoding logic.

[0094] 2.4 DSP Interaction Interface

[0095] The DSP treats the FPGA as an external memory. When writing control data, the DSP only needs to continuously write 36 duty cycle data points into the designated address segment of Zone7 (corresponding to the RAM write area). When reading status data, the DSP only needs to perform a burst read from another address segment of Zone7 to obtain the latest status of all 36 cells. Since all data transfer and protocol processing are completed in parallel by the FPGA hardware, the time taken for each of the DSP's two operations is no more than a few microseconds.

[0096] In downlink data processing, the expression for calculating the read address using the FPGA is:

[0097] (1)

[0098] In the formula, This represents the read address of the dual-port RAM (dimensionless), ranging from 0 to 35; This indicates the logical group identifier (dimensionless), for example: U phase = 0, V phase = 1, W phase = 2; This indicates the unit number within the group (dimensionless), ranging from 0 to 11.

[0099] During the uplink reception bit synchronization process, the relationship between the sampling clock frequency and the Manchester symbol rate is expressed as follows:

[0100] (2)

[0101] (3)

[0102] In the formula, This indicates the clock frequency (in Hz) used internally by the FPGA for edge detection and sampling. Symbol rate for Manchester encoding (unit: baud, Bd); This represents the oversampling factor (dimensionless), typically 8 or 16, to ensure reliable detection of symbol edges; The sampling clock period (unit: seconds, s).

[0103] Continuing, three different levels of implementation examples are constructed, each with its own focus and progressively deeper.

[0104] Example 1: Basic Implementation (for a three-phase 36-unit system)

[0105] This embodiment details the specific application of the invention in a typical scenario of controlling 36 units in a 13.8kV system, demonstrating how the core modules work together.

[0106] S1.1 System Hardware Architecture

[0107] Table S1-1 is a simplified table of the core parameters of the system's hardware architecture.

[0108] Table S1-1 Simplified Table of Core Parameters of the System Hardware Architecture

[0109] Module Core parameters Main controller TI TMS320F28335 DSP, 150MHz clock speed coprocessor Lattice LFXP2-17E-6QN208C FPGA (as I / O expander) DSP-FPGA communication XINTF Zone7, 16-bit data width, 20-bit address lines. Fibre Channel Downlink: 36 channels 850nm multimode; Uplink: 36 channels 1310nm single-mode; Encoding: Manchester; Baud rate: 2.5Mbps

[0110] S1.2 Detailed Logic Design of the FPGA

[0111] S1.2.1 Address Space Mapping Table

[0112] The memory space inside the FPGA that is mapped to the DSP is shown in Table S1-2.

[0113] Table S1-2 shows the internal memory space of the FPGA that is mapped to the DSP.

[0114] XINTFZone7 starting address FPGA internal mapping module Size (of characters) Access methods Function Description 0x100000 Control / Status Register 4 DSP Read / Write Includes ping-pong buffer switching flag, global enable, fault status, etc. 0x100004 Downlink data write area (DSP->FPGA) 36 DSP writing The DSP writes duty cycle instructions for 36 cells consecutively to this region. The FPGA directs these instructions to the write port of RAM_A or RAM_B based on the ping-pong flag. 0x100028 Uplink data read area (FPGA->DSP) 36 DSP Read The DSP can read the latest status words from 36 cells at once from this area. The FPGA synchronizes the status register array to this area in real time. 0x10004C Unit Independent Configuration Area 36 DSP Read / Write The communication timeout threshold and enable bit can be configured for each unit.

[0115] S1.2.2 Downlink Ping-Pong Buffer State Machine Flowchart

[0116] like Figure 4 As shown, the downlink data processing of this invention adopts the classic ping-pong buffer strategy, but its innovation lies in its deep integration with the parallel transmission logic of the FPGA and the memory mapping interface of the DSP. Its operation method revolves around the alternation of two core states (WRITE_TO_A and WRITE_TO_B), ensuring that data production (DSP writing) and data consumption (FPGA transmission) are completely parallel and do not block each other.

[0117] The operation steps are as follows:

[0118] Step 1: Initial state (IDLE -> WRITE_TO_A).

[0119] Step 1.1: After the DSP enables the system, the state machine enters the WRITE_TO_A state. At this time, RAM_A is defined as the "write area" and RAM_B is defined as the "read area".

[0120] Step 1.2: Parallel operation begins: The DSP writes the duty cycle data of the 36 units for the next control cycle into the address space of RAM_A mapped to the FPGA via the XINTF bus. Simultaneously, the FPGA's transmission logic core automatically reads the data of the current control cycle from RAM_B, groups and encodes it, and transmits it through 36 optical fibers.

[0121] Step 2: Continuous parallel operation in state A (WRITE_TO_A state). This is a stable operating state. The system maintains this state as long as the DSP has not finished writing new data and the FPGA has not finished sending old data. The key point is that the DSP's write operation and the FPGA's read / send operation are physically simultaneous, accessing different physical memory blocks (RAM_A and RAM_B) respectively. Therefore, there are no bus conflicts or waiting, achieving 100% hardware parallel efficiency.

[0122] Step 3: State Switching Condition Judgment (SWITCH_AB). The sole condition for switching is that both the "DSP write complete" and "FPGA transmit complete" events are simultaneously satisfied. This is a hardware synchronization point. "DSP write complete" is typically notified to the FPGA by the DSP setting a specific flag, or automatically detected by the FPGA through address counting. "FPGA transmit complete" is generated by the FPGA's internal transmit state machine after completing the transmission of the last frame. This judgment mechanism ensures data integrity and strict period alignment, preventing data overwriting or transmission interruption.

[0123] Step 4: Role Switching (WRITE_TO_A -> WRITE_TO_B). When the switching condition is met, the state machine enters the WRITE_TO_B state. At this time, the functional roles of RAM_A and RAM_B are immediately swapped.

[0124] Step 4.1: RAM_A becomes the new "read area", which stores the latest data just written by the DSP.

[0125] Step 4.2: RAM_B becomes the new "write area", ready to receive data from the DSP in the next cycle.

[0126] Step 5: Then, a new round of parallel operations begins: the DSP starts writing the data for the next cycle to RAM_B, while the FPGA reads the latest data from RAM_A and sends it.

[0127] Step 6: Looping and exception handling.

[0128] Step 6.1: The system will cycle between the two states WRITE_TO_A and WRITE_TO_B to form a continuous pipeline.

[0129] Step 6.2: The "DSP prohibits sending" path in the flowchart points to the IDLE state, indicating that the mechanism is controllable. In the event of a system failure or the need for a shutdown, the DSP can issue a command to return the state machine to the idle state, and the process will terminate safely.

[0130] S1.2.3 Uplink Parallel Decoding Timing Analysis

[0131] The key to uplink decoding lies in bit synchronization. Manchester code involves a transition in the middle of each bit. The FPGA uses 80MHz ( The master clock samples the RX signal. The expression for the oversampling factor is:

[0132] (4)

[0133] The edge detection window detects level changes across 32 consecutive sampling points. When a change is detected, the "majority vote" value within the two 16-sample windows before and after the change point is used as the symbol decision result, effectively suppressing glitches.

[0134] For the Road signal, its first One received byte By shift register The bits in the calculation are used to arrive at the decoding formula, which is:

[0135] (5)

[0136] In the formula, yes The decoded first The first byte Bit (value is 0 or 1) This indicates a left shift operation.

[0137] S1.3 Software Interaction Flow

[0138] like Figure 5 As shown:

[0139] Step 1: Initialization, configure the XINTF timing of the DSP, and write the global enable to the FPGA control register.

[0140] Step 2: Main control loop.

[0141] Step 2.1: The DSP calculates the new duty cycle for the 36 units.

[0142] Step 2.2: The DSP checks the "Buffer Ready" flag in the FPGA status register.

[0143] Step 2.3: Once ready, the DSP quickly writes 36 data words (contiguous addresses) into the "downlink data write area" mapped by the FPGA via memcpy or DMA.

[0144] Step 2.4: The DSP bursts to read 36 status words from the "uplink data read area" for fault diagnosis and control in the next cycle.

[0145] Step 3: Exception Handling. If the timeout flag is set in the status word read by the DSP, an interrupt is triggered, and the predetermined fault-safe strategy is executed.

[0146] Example 2: Extended Implementation (Supports Variable Grouping and Dynamic Reconfiguration)

[0147] Based on Example 1, this embodiment adds flexible grouping and dynamic configuration of communication parameters, enabling the system to adapt to different scales (such as 24 or 48 units) and different communication rates.

[0148] S2.1 Variable Packet Logic

[0149] The FPGA no longer uses a fixed 3 x 12 cells internally, but instead defines the number of cells through configuration registers. and the number of units in each group And satisfy:

[0150] (6)

[0151] The method of group configuration register is as follows: a 32-bit group configuration register is designed inside the FPGA. Its high 4 bits [31:28] are used to configure the total number of groups M (ranging from 1 to 16), the middle two 12-bit fields [27:16] and [15:4] are used to dynamically configure the number of units N0 and N1 of group 0 and group 1, respectively, and the low 4 bits [3:0] are reserved for later use, thus realizing flexible and variable group logic.

[0152] When the FPGA reads RAM, the dynamic address is dynamically calculated by the block mapping logic; that is, the expression for generating the dynamic address is:

[0153] (7)

[0154] (8)

[0155] In the formula, This is the current processing group number. This is the group number.

[0156] S2.2 Configurable Communication Protocol Timing

[0157] To ensure compatibility with different transmission distances and fiber optic types, the FPGA supports online configuration of baud rate and frame structure. Internally, the FPGA generates the bit clock via a programmable frequency divider. This enables baud rate generation, i.e.

[0158] (9)

[0159] DSP will require The value is written to the configuration register, and the FPGA automatically calculates and updates it. The programmable frame structure is as follows: the downlink frame header, data bit length, and checksum method can be configured via registers. For example, the data bits can be configured from 8 bits to 16 bits to accommodate higher precision control commands.

[0160] S2.3 Dynamic Reconstruction Method

[0161] like Figure 6 As shown, the FPGA receives configuration commands from the DSP and dynamically adjusts its internal processing logic to adapt to new task requirements. Specifically, after the DSP sends a configuration command to the FPGA containing the grouping mode (grouping rules such as M, N0 / N1), a baud rate of 1.25 Mbps, and a data width of 16 bits, the FPGA distributes the parameters to the grouping calculator, baud rate generator, and frame assembly state machine through the "configuration parsing and parameter loading module" for corresponding adjustments. Then, the "dynamic logic reconfiguration area" modifies the internal hardware logic in real time, ultimately achieving dynamic adaptation of communication rules, allowing the system to flexibly match the grouping and communication parameter requirements of different controlled units.

[0162] Example 3: Optimized Implementation (Integrated Hardware Fault Diagnosis and Preprocessing)

[0163] This embodiment, based on the previous two embodiments, further integrates advanced fault diagnosis functions, implements some diagnostic algorithms in hardware, further reduces the burden on the DSP, and improves system reliability.

[0164] S3.1 Hardware Timeout and CRC Check

[0165] The FPGA integrates a hardware-level communication guarantee mechanism, namely, each uplink channel is equipped with an independent 32-bit timeout counter, which accumulates when there is no valid frame. When the threshold is exceeded, the "communication timeout" flag is automatically set and an interrupt can be triggered optionally. At the same time, a CRC8 checksum is automatically attached before downlink transmission. The uplink receiver completes automatic verification. If the verification fails, the "data error" flag is immediately set. No DSP intervention is required throughout the process, realizing efficient and reliable autonomous fault diagnosis.

[0166] S3.2 State Change Rate Monitoring (Hardware Implementation)

[0167] To prevent abnormal state transitions in the FPGA, the rate of change monitoring logic is built-in. For the first... The state value of each unit The FPGA stores its previous cycle value. And calculate the change as follows:

[0168] (10)

[0169] Compare this change with the DSP's preset threshold. Comparison, that is

[0170] (11)

[0171] This comparison operation is performed in parallel across 36 channels and completed within one clock cycle. Alarm flags are integrated into the status word for the DSP to read.

[0172] S3.3 Fault Data Snapshot Cache

[0173] When any channel's "communication timeout," "data error," or "rate of change alarm" flag is triggered, the FPGA automatically stores the current data and the raw data from the previous few cycles for that channel into a dedicated, cyclically overwritten fault snapshot RAM. Simultaneously, it records the fault timestamp and channel number. Upon receiving an interrupt, the DSP can read detailed fault context information from this RAM for in-depth analysis without losing critical transient fault data due to interrupt processing delays.

[0174] S3.4 Comparison and Analysis of Effects

[0175] S3-1 indicates the comparison of effects.

[0176] S3-1 Effect Comparison

[0177] Diagnostic function Software implementation (traditional method) Hardware implementation (in this embodiment) Advantages 36-channel communication timeout detection The DSP needs to poll and read 36 states, then compare them with the system time, which takes more than 100µs. FPGA parallel comparison, real-time flag update, DSP direct reading, time consumption ≈ 0 Real-time performance greatly improved 36-channel CRC check The DSP needs to perform 36 CRC calculations in a loop, consuming a large number of CPU cycles. FPGA transmit and receive operations are completed automatically with zero CPU overhead. Unleash DSP computing power Monitoring of the rate of change of state The DSP needs to cache the data from the previous cycle and perform 36 subtractions and comparisons, resulting in a large computational latency. The FPGA performs all comparisons in parallel within one clock cycle. Achieve true real-time monitoring Fault Transient Capture Difficult to implement, or relies on additional peripherals, resulting in high costs. Implemented using FPGA internal RAM, it is low-cost and provides complete information. Improve system maintainability

[0178] This invention has been described through several embodiments. Those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of this invention, modifications can be made to these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention.

Claims

1. A high-speed communication method for multiple units of CHB frequency converters based on FPGA ping-pong buffer, characterized in that: After initialization, configuring the DSP XINTF timing, and writing the global enable to the FPGA control register, the following steps are performed: Step 1: Main control loop. The FPGA internally allocates two dual-port Block RAMs, namely RAM_A and RAM_B. The DSP writes the duty cycle of the next cycle of the 36 units calculated by the DSP into RAM_A through the external parallel bus. At the same time, the FPGA's transmission logic reads the data of the current control cycle from the other RAM (RAM_B) and encodes and sends it. After one cycle, the "read / write" roles of the two RAMs are switched through a hardware handshake signal, and so on. Step 2: Unit status acquisition. The FPGA's input I / O samples the encoded signals of all uplink fiber channel inputs in parallel. The corresponding shift registers perform serial data reception and serial-to-parallel conversion, decode and extract the original status data of each power unit, and update it to the global status register array in real time. This status register array is linearly mapped to the DSP's external memory interface. The DSP calculates the duty cycle of the next cycle of 36 units based on the read status of each power unit. Step 3: Anomaly handling involves hardware-based diagnostic algorithms for the FPGA, which are then used in conjunction with the DSP for fault detection.

2. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 1, characterized in that: The unit status acquisition steps include the following steps: Step 1.1: Start the process and enter the judgment phase; Step 1.2: Determine if both "DSP write complete" and "FPGA send complete" are met simultaneously; if yes, switch RAM roles (RAM_A and RAM_B swap "read area / write area"); if no, proceed to the next step. Step 1.3: FPGA reads data from the current read area RAM (e.g., RAM_B) and reads the control data that needs to be sent to all units in the current cycle in parallel; Step 1.4: FPGA processing, data is grouped and encoded in parallel, and then transmitted; Step 1.5: DSP writing (performed simultaneously with Step 2.3 and Step 2.4), writing the next cycle of data to the current write area RAM (e.g., RAM_A). Step 1.6: Loop back to the judgment step and repeat the process.

3. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 2, characterized in that: The status acquisition step of Unit 1 also includes loop and exception handling steps. When the system fails or needs to be shut down, the DSP can issue an instruction to stop the FPGA from sending encoding to each power unit, and the main control loop process is safely terminated.

4. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 3, characterized in that: The FPGA internally defines the number of groups M and the number of cells N in each group through configuration registers. i In the FPGA reading step of Step 1.3, the FPGA performs parallel-to-serial conversion on the read data according to the group mapping logic, and encapsulates it into fiber optic protocol frames such as Manchester encoding, and drives all downlink fiber optic channels in parallel through physical I / O.

5. The CHB frequency converter multi-unit high-speed communication system based on FPGA ping-pong buffer according to claim 4, characterized in that: The unit status acquisition steps specifically include the following steps: Step 2.1: The FPGA's input I / O samples the Manchester-coded signals from all uplink fiber channel inputs in parallel; Step 2.2: For each signal, a dedicated edge detection circuit restores the output synchronization clock and controls the corresponding shift register to perform serial data reception and serial-to-parallel conversion; Step 2.3: The Manchester decoding logic extracts the original state data of each power unit in parallel from the shift register and updates it to the global state register array in real time; Step 2.4: The status register array is linearly mapped to the DSP's external memory interface.

6. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 1, characterized in that: The exception handling steps include: Step 3.1: Hardware timeout and CRC check; Step 3.1.1: The FPGA uplink channel is equipped with an independent 32-bit timeout counter, which accumulates when there is no valid frame. When the threshold is exceeded, the "communication timeout" flag is automatically set and an interrupt can be triggered optionally. Step 3.1.2: The FPGA automatically adds a CRC8 checksum before downlink transmission. The uplink receiver completes automatic verification. If the verification fails, the "data error" flag is immediately set.

7. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 6, characterized in that: The exception handling steps also include: Step 3.2: Monitoring the rate of change of state (hardware implementation); Step 3.2.1: FPGA built-in rate of change monitoring logic. For the first... The state value of each unit The FPGA stores its previous cycle value. And calculate the change: Step 3.2.2: Calculate the change amount , compared with the DSP preset threshold Comparison, that is This comparison operation is performed in parallel across 36 channels and completed within one clock cycle. The alarm flag is integrated into the status word for the DSP to read.

8. The high-speed communication method for multiple units of CHB frequency converter based on FPGA ping-pong buffer according to claim 7, characterized in that: The exception handling steps also include: Step 3.3: Fault data snapshot caching; Step 3.3.1: When the "communication timeout", "data error" or "rate of change alarm" flag of any channel is triggered, the FPGA automatically stores the raw data of the current time and the previous few cycles of that channel into a dedicated, cyclically overwritten fault snapshot RAM. Step 3.3.2: Record the fault timestamp and channel number (do this simultaneously with Step 3.3.1).

9. A high-speed communication system for multiple units of a CHB frequency converter based on FPGA ping-pong buffer for implementing the method of any one of claims 1-8, characterized in that: include: DSP: As the control core, it directly accesses the memory area mapped inside the FPGA through the external memory interface; FPGA: It integrates three core modules: a status register array, a ping-pong dual-port RAM, and a packet encoding / decoding logic, which are responsible for status buffering, instruction buffering, and fiber optic protocol conversion, respectively. Controlled units: There are 36 units, each connected to the FPGA via an independent fiber optic channel; The DSP is connected to the FPGA via its external interface's 16-bit data bus, address bus, and control lines.

10. The CHB frequency converter multi-unit high-speed communication system based on FPGA ping-pong buffer according to claim 9, characterized in that: Each uplink channel of the FPGA is equipped with an independent 32-bit timeout counter, and the FPGA has built-in change rate monitoring logic.

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