A Synchronous Control Method Based on FPGA

Abstract

The present invention belongs to the field of digital circuit technology, and proposes a synchronous control method based on FPGA, which includes: FPGA logic determines whether the synchronization condition is met, if it is met, then the logic controls two devices to be synchronized to each send out a first synchronization indication signal, and continuously collects the synchronization indication signal sent by the other device until the first synchronization is achieved; after the first synchronization is achieved, the logic controls the two devices to be synchronized to each send out a second synchronization indication signal, and continuously collects the synchronization indication signal of the other device until the second synchronization is achieved; when the synchronization is achieved, the logic controls the two devices to control the wing movement at the same time. The present invention can execute a set of established synchronous control strategies through FPGA when the conditions for folding / unfolding the left and right wings cannot be met at the same time, thereby quickly and accurately realizing the synchronous output of the left and right wings, and significantly improving the control timeliness and product reliability.

Description

Technical Field

[0001] The present disclosure relates to the technical field of digital circuits, and in particular to a synchronous control method based on FPGA. Background Art

[0002] The left and right wings are controlled by two remote interface units (hereinafter referred to as RIU) distributed on the left and right sides of the fuselage respectively. Since the conditions for synchronous control are relatively complex, they generally include: wheel-loaded signals, wing folding handle status signals, folding solenoid valve control instructions, etc. These signals are transmitted by different devices through different buses. For example, the wheel-loaded signals are sent by the CPU through the SPI bus, and the folding solenoid valve control instructions are sent by the manual / automatic control box through the HB6096 bus. Since the signals of the manual / automatic control box are asynchronous, the synchronization conditions of RIU1 and RIU2 are also asynchronous, making it impossible to control the synchronous folding or unfolding of the left and right wings.

[0003] In view of the above problems, the solutions in the prior art generally rely on the RIU application software to judge the synchronization conditions, thereby controlling the wing output. However, due to the long software operation cycle, generally 5-10ms, the judgment and control delays are large, and the synchronization control effect is poor. Summary of the invention

[0004] In view of this, the embodiment of the present disclosure provides a synchronous control method based on FPGA, which makes full use of the parallel working timing and high-speed clock characteristics of FPGA, and designs a set of synchronous control strategies. When the conditions for folding / unfolding the left and right wings cannot be met at the same time, a set of established synchronous control strategies can be executed through FPGA, thereby quickly and accurately realizing the synchronous output of the left and right wings, significantly improving the control timeliness and product reliability.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A synchronous control method based on FPGA, comprising the following steps:

[0007] Step 1: FPGA logic determines whether the synchronization condition is met. If so, it proceeds to step 2;

[0008] Step 2: Logically control the two devices to be synchronized to send out the first synchronization indication signal respectively, and continue to collect the synchronization indication signal sent by the other device until the first synchronization is achieved;

[0009] Step 3: After the first synchronization is achieved, the two devices to be synchronized are logically controlled to each send out a second synchronization indication signal, and continue to collect the synchronization indication signal of the other device until the second synchronization is achieved;

[0010] Step 4: Achieve synchronization and logically control the two devices to control the wing movements simultaneously.

[0011] Furthermore, there is a hard-wire signal connection between the two devices to be synchronized, which is used to transmit a synchronization indication signal.

[0012] Furthermore, in step 1, the triggering conditions of the synchronization condition control logic are input by multiple types of signals via different data transmission buses and IO ports, and the signals are diverse and asynchronous.

[0013] Furthermore, in step 2, the first synchronization indication signal sent by the logic lasts for at least 500us to ensure that the synchronization indication signal sent by the other party is correctly collected.

[0014] Furthermore, in step 3, the logic sends out a second synchronization indication signal, and when the synchronization indication signal sent by the other party is collected, the synchronization is immediately completed.

[0015] Furthermore, in step 4, the synchronization flag in the logic is set to "1" and the output of the wing solenoid valve is controlled at the same time. After the synchronization control logic ends, the flag is reset to "0".

[0016] Furthermore, when the first synchronization or the second synchronization is not achieved, the logic does not take action. After the CPU determines that the synchronization control is not output, the CPU starts the synchronization instruction again, and the logic re-executes steps 1 to 4 until the two devices can achieve synchronous output.

[0017] Furthermore, the same logic is programmed into the FPGAs of the two devices to be synchronized.

[0018] Furthermore, the control output time difference between the two devices to be synchronized is at nanosecond level.

[0019] The present invention provides a synchronous control method based on FPGA. When the conditions for synchronous folding / unfolding of the left and right wings cannot be achieved at the same time, the parallel timing of FPGA is used to implement a set of synchronous control strategies under a 30M clock. Compared with traditional software control, the control cycle can be greatly shortened and the control accuracy can be improved, and the control timeliness and product reliability can be significantly improved, thereby quickly and accurately realizing the synchronous output of the left and right wings and ensuring the consistency of the left and right wing movements. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a schematic diagram of the synchronous control function structure of the present invention;

[0022] Figure 2 It is a schematic diagram of the synchronous control timing of the present invention. DETAILED DESCRIPTION

[0023] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0024] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0025] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The drawings only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0028] The disclosed embodiment provides a synchronous control method based on FPGA, which utilizes the parallel timing of FPGA to implement a set of synchronous control strategies under a 30M clock, thereby quickly and accurately realizing the synchronous output of the left and right wings.

[0029] The synchronous control method specifically comprises the following steps:

[0030] Step 1 Synchronization conditions: The device RIU1 logic automatically determines whether the synchronization control (folding / unfolding) conditions are met. The synchronization conditions are as follows: Figure 1 If it is satisfied, go to step 2;

[0031] Step 2: First synchronization: The synchronization signal 1 output of the device RIU1 is folded. If the folded signal output by the synchronization signal 2 of the device RIU2 is collected, the first synchronization is achieved;

[0032] Step 3: Second synchronization: The synchronization signal 1 of the device RIU1 outputs the median. If the median signal output by the synchronization signal 2 of the device RIU2 is collected, the second synchronization is achieved.

[0033] Step 4: Synchronous output: After both synchronizations in steps 2 and 3 are achieved, the FPGA of device RIU1 and device RIU2 controls the left and right wing folding solenoid valves to output "fold".

[0034] Among them, preferably, considering the acquisition period of discrete quantities, the acquisition time of the synchronous folding signal in step 2 should meet ≥500us.

[0035] The device RIU1 and the device RIU2 are not divided into master and slave, that is, in step 2, RIU2 can initiate the first synchronization first, and the same logic can be burned to achieve synchronous folding / unfolding control.

[0036] The synchronous control method can realize the synchronous folding or unfolding control of the left and right wings by the remote interface unit devices RIU1 and RIU2 distributed on both sides of the left and right wings. Two hard-wire signals are added between the two RIUs, and the two signals serve as the output of the local RIU and the input of the other end RIU. When the conditions for folding / unfolding the wings are met, a set of synchronous control strategies is implemented using FPGA. When the first synchronization and the second synchronization are both achieved, the FPGA controls the wing to fold or unfold. This embodiment effectively utilizes the concurrency of the FPGA working timing. When the folding / unfolding conditions of the two RIUs cannot be achieved at the same time, the left and right wings can still maintain synchronous movement. The two RIUs are not divided into master and slave, and synchronous control can be achieved by burning the same logic. Compared with software control, it can greatly shorten the control cycle and improve the control accuracy.

[0037] The present embodiment is further described below in conjunction with the accompanying drawings.

[0038] like Figure 1 As shown, Figure 1 Provides a synchronous control trigger condition based on FPGA and the relationship between various signals. Figure 1 Device RIU1 and device RIU2 in the control the left wing folding solenoid valve and the right wing folding solenoid valve respectively. The trigger conditions for controlling the wing folding / unfolding are: wheel load signal, wing folding handle status signal, override switch-on signal, folding solenoid valve control command, etc. Among them, the wheel load signal, wing folding handle status signal, and override switch-on signal are sent to the FPGA of RIU1 and RIU2 by the SPI bus, and the folding solenoid valve control command is transmitted by the manual / automatic control box through the HB6096 bus. Device RIU1 and device RIU2 are connected by two hard-wire signals, synchronization signal 1 and synchronization signal 2. Synchronization signal 1 is the output of device RIU1 and the input of device RIU2. Similarly, synchronization signal 2 is the output of device RIU2 and the input of device RIU1.

[0039] In this embodiment, the above trigger conditions are diverse;

[0040] Each trigger condition is transmitted by different types of buses;

[0041] Optionally, the left and right wing trigger conditions cannot be achieved synchronously and are asynchronous;

[0042] The functional structure of this embodiment is further explained by taking synchronous folding control as an example. When the wheel load (SPI input) is on the ground and the override is not turned on (HB6096 input), the automatic mode is entered. In this mode, the wing foldable state (SPI input) is "foldable" and the folding handle state (SPI input) is folded. When all the above conditions are met, the wing folding control instruction from HB6096 is folding, and the synchronous control logic is started. The synchronous output signal consists of two hard-wire signals. The device on this side collects the synchronous signal sent by the other device through the discrete quantity chip, and the collection delay is no more than 250us.

[0043] like Figure 2 As shown, Figure 2 The working sequence of this embodiment is provided. Taking the device RIU1 starting synchronization as an example, the sequence of the synchronization control logic is described.

[0044] When the synchronization condition is met, the synchronization control logic is triggered, such as Figure 2 As shown in the mark ①. The synchronization signal 1 of the device RIU1 outputs a high level, which will be maintained for at least 500us. At the same time, the synchronization control logic of the device RIU2 is also triggered, and the synchronization signal 2 of the device RIU2 outputs a high level.

[0045] When the synchronization control logic is triggered, both device RIU1 and device RIU2 are collecting discrete quantities at the same time. When device RIU1 collects the synchronization signal 2 sent by device RIU2 as a high level (collection delay ≤ 250us), and the synchronization signal 1 sent by device RIU1 outputs a high level for a time that is ≥ 500us, the first synchronization of device RIU1 is completed. Figure 2 At the same time, the device RIU2 also collects the synchronization signal 1 sent by the device RIU1 as a high level. When the synchronization signal 2 sent by the device RIU2 outputs a high level and the holding time meets ≥500us, the first synchronization of the device RIU2 is completed.

[0046] After the first synchronization is achieved, the synchronization signal 1 of the device RIU1 outputs a low level. When the synchronization signal 2 sent by the device RIU2 is collected as a low level, the second synchronization of the device RIU1 is achieved. Figure 2 As shown in the mark ③. At the same time, the device RIU2 also collects the synchronization signal 1 sent by the device RIU1 as a low level, and the second synchronization of the device RIU2 is achieved. At this time. The synchronization flag in the logic is set to "1", and the wing folding solenoid valve outputs "fold" or "unfold".

[0047] The present invention effectively utilizes the parallel timing of FPGA. Under the premise that the conditions for synchronous folding / unfolding of the left and right wings cannot be achieved at the same time, a set of synchronous control strategies is implemented using a logical 30M high-speed clock to control the output difference between the device RIU1 and the device RIU2 to the nanosecond level. Thus, the synchronous output of the left and right wings is achieved quickly and accurately, ensuring the consistency of the left and right wing movements. Regardless of master or slave, the device RIU1 and the device RIU2 can both initiate the first synchronization first, and synchronous folding / unfolding control can be achieved by burning the same logic.

[0048] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A synchronous control method based on FPGA, characterized in that: The following steps are involved: Step 1: FPGA determines whether the synchronization condition is met. If so, it proceeds to step 2; Step 2: FPGA controls the two devices to be synchronized to send out the first synchronization indication signal respectively, and continuously collects the synchronization indication signal sent by the other device until the first synchronization is achieved; Step 3: After the first synchronization is achieved, the FPGA controls the two devices to be synchronized to send out the second synchronization indication signal respectively, and continues to collect the synchronization indication signal of the other device until the second synchronization is achieved; Step 4: Achieve synchronization, FPGA controls the two devices to control the wing movement simultaneously; There is a hard-wire signal connection between the two devices to be synchronized, for transmitting a synchronization indication signal; In step 2, the time for the first synchronization indication signal sent by the FPGA is at least 500us to ensure that the synchronization indication signal sent by the other party is correctly collected; In step 3, the FPGA sends a second synchronization indication signal, and when the synchronization indication signal sent by the other party is collected, the synchronization is completed; The same software is burned on the FPGA of the two devices to be synchronized; and the control output time difference of the two devices to be synchronized is in nanosecond level.

2. The FPGA-based synchronous control method according to claim 1, characterized in that: In step 1, the triggering conditions of the synchronous control of the FPGA are input by multiple types of signals via different data transmission buses and IO ports.

3. The FPGA-based synchronous control method according to claim 1, characterized in that: In step 4, the synchronization flag position in the FPGA is "1", and the output of the wing solenoid valve is controlled at the same time. After the synchronization control logic ends, the flag position is reset to "0".

4. The FPGA-based synchronous control method according to claim 1, characterized in that: When the first synchronization or the second synchronization is not achieved, the FPGA does not take any action. After the CPU determines that the synchronization control is not output, the CPU starts the synchronization instruction again, and the FPGA re-executes the steps 1 to 4 until the two devices can achieve synchronous output.

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