Method and system for improving motor control performance based on MPSoC technology

Abstract

The invention relates to the technical field of electromechanical control, in particular to a method and system for improving motor control performance based on the MPSoC technology, and the system comprises a motor body, an MPSoC chip and an upper computer. The MPSoC chip comprises a PL module and a PS module; the PL module is used as an FPGA structure, and the PS module is used as an MCU structure; the PL module and the PS module are connected through an AXI bus in the chip and carry out information interaction; the PL module is connected with the motor body, and the PS module is connected with the upper computer; according to the electric drive control system, the MPSoC chip is used as an electric drive control main body, so that the control period and the fault protection response time are reduced, and the response efficiency of the electric drive control system is improved.

Description

Technical Field

[0001] The present invention relates to the field of electromechanical control technology, and specifically to a method and system for improving motor control performance based on MPSoC technology. Background Art

[0002] With the popularization of new energy vehicles, the real-time requirements of electric drive control systems are becoming increasingly higher. Especially with the rapid development of new power switching devices such as SiC, the corresponding switching frequency will also increase from about 10KHz to 20KHz or even above 30KHz.

[0003] The electric drive control system mainly consists of motors, power devices and control systems. The electric drive control system is one of the core technologies of new energy vehicles. Its main task is to efficiently convert the chemical energy of the power battery into mechanical energy according to the driver's driving intention.

[0004] With the rapid development of power switch devices, the electric drive control system based on the traditional microcontroller MCU is limited by the performance of the MCU and generally only has a response speed of about 100us. Therefore, the fault response and processing time is also relatively long, and protection within 10us cannot be achieved.

[0005] To this end, the prior art proposes an integrated optimization method for the structure and control of a motor drive system. The invention obtains the global optimal design parameters of the system through an optimization strategy that combines a nested optimization method with a fruit fly optimization algorithm, thereby improving the control performance. However, the problem of rapid response of the electric drive control system is still not solved.

[0006] In view of this, we propose a method and system to improve motor control performance based on MPSoC technology. Summary of the invention

[0007] The purpose of the present invention is to provide a method and system for improving motor control performance based on MPSoC technology to solve the problems raised in the above background technology.

[0008] To achieve the above object, the present invention provides the following technical solutions: The system based on MPSoC technology to improve motor control performance includes a motor, an MPSoC chip, and a host computer; The MPSoC chip includes a PL module and a PS module; the PL module is an FPGA structure, which is a built-in FPGA structure part of the chip and is used to implement the electric drive control algorithm. The FPGA structure is a product further developed on the basis of programmable devices such as programmable array logic and general array logic, and is mainly used as a semi-custom circuit in the field of application-specific integrated circuits; The PS module is an MCU structure, which is a microcontroller unit that integrates a series of computer peripheral interfaces, storage, processor and clock circuits, and has control, calculation and communication capabilities; the PS module only performs communication functions with the host computer and data storage functions; The PL module and the PS module are connected through the AXI bus inside the chip and exchange information; the PL module is connected to the motor body, and the PS module is connected to the host computer; with MPSoC as the core control chip, interaction with the host computer and control of the motor body are realized, and then the electric drive control algorithm and fault protection are realized, thereby improving the response time of the electric drive control; The host computer is used to interact with the user. As a bridge between the user and the electric drive control system, the host computer transmits the user's instructions to the MPSoC chip for real-time feedback, and provides the data obtained by the electric drive control system for the user's reference, thereby realizing two-way interaction.

[0009] Preferably, the PS module adopts a built-in ARM R5 chip, and the PS module realizes the CAN communication function with the host computer based on the commonly used automobile communication XCP protocol. The PS uses the built-in ARM R5 chip as the MCU structure, and realizes the communication function through the commonly used automobile communication XCP protocol. The PS module serves as a connecting bridge between the host computer and the PL module, and realizes data interaction between the host computer and the PL.

[0010] Preferably, the PL module includes an application software layer ASW and a basic software layer BSW; the application software layer ASW mainly implements the motor control algorithm and the timing control between the modules; the basic software layer BSW mainly implements signal acquisition and PWM output; the basic software layer BSW performs data acquisition on current, voltage and temperature, and during the acquisition process, the data acquisition sequence is controlled through the application software layer ASW, and PWM output is performed according to the collected data.

[0011] Furthermore, the application software layer ASW includes an MDCM module and a Timing module; The MDCM module is a motor drive module, which includes signal filtering, fault diagnosis, torque control and current control functions; the MDCM module is a general motor control algorithm module, and all its functions are implemented by using FPGA to improve computing performance, reduce computing time, and reduce the computing burden of MCU; The Timing module is a timing management module that controls the MDCM module and the basic software layer BSW. Since the hardware structure generated by the FPGA structure is calculated in parallel, the asynchronous calculation delays on different paths may lead to target data calculation errors. Therefore, the designed Timing module is used to perform timing control to ensure the correctness of the calculation.

[0012] Furthermore, the MDCM module is divided into three tasks, and the tasks are divided into different priorities for calculation. The three tasks are 100us, 1ms and 10ms respectively, and correspond to the current algorithm module, the voltage algorithm module and the temperature algorithm module in turn; The priorities of the current algorithm are current signal filtering, current signal fault and current closed-loop control; the priorities of the voltage algorithm are voltage signal filtering, voltage signal fault and speed signal fault; the priorities of the temperature algorithm are temperature signal filtering, temperature signal fault and torque control; The Timing module performs parallel tasks on three tasks or runs the algorithm modules within a single task in parallel.

[0013] Preferably, the basic software layer BSW includes ADC sampling, resolver module and PWM wave generation; The ADC sampling is to sample the three-phase current of the motor, the bus voltage of the electric drive and the temperature of the motor. The ADC sampling is to trigger the external ADC chip by outputting a sampling trigger signal at a fixed frequency, perform data conversion through the ADC chip, and then read the converted data; The resolver module controls the hard decoding chip to obtain the position and speed signals of the motor body; The PWM wave is output by calculating the duty cycle duty through the algorithm of the application software layer ASW, and the dead zone interval is configured. The sampled data is calculated through the motor control algorithm to generate a PWM signal. The PWM signal is a digital signal, and its pulse width will change according to the change of the input signal or the control signal; the pulse width is the duration of the high level. The protection effect of the electric drive control system is improved by configuring the dead zone interval.

[0014] A method comprising the following steps: Step 1: Power on the motor body, which transmits current to the MPSoC chip. The PS module in the MPSoC chip starts its own program to connect with the host computer to realize the communication function. The PL module loads the program, and the application software layer ASW and the basic software layer BSW are started. The MPSoC chip is reset and initialized. Step 2: The PS module interacts with the host computer, receives instructions from the host computer and passes them to the PL. The user inputs his own instructions through the host computer. After receiving the instructions, the host computer passes them to the PS module through the CAN communication of the car. The PS module passes the instructions to the PL module through the AXI bus. Step 3: The PL module changes state according to the received instruction; Step 4: The PL module runs the corresponding algorithm program according to the instructions, system status and sampled data. The PL module collects the data of the motor body and transmits the collected data to the algorithm program. The PL module also performs real-time detection and fault detection on the current, voltage and temperature of the motor body according to the algorithm program. Step 5: If the PL module detects a fault, it will perform fault processing and enter the corresponding system state. The PL module calculates the collected signals to determine the fault problem and transmits the signal to the host computer through the PS module for the user to view; Step 6: If the PS module receives a shutdown command, it sends it to the PL module to make it go through the shutdown process. The PL module turns off the output, the PS module saves the data, and then powers off to stop driving the motor body.

[0015] Preferably, step 4 comprises the following steps: Step 4.1: The PL module performs ADC sampling and resolver sampling through the basic software layer BSW; Step 4.2: At the same time, the Timing module in the application software layer ASW performs timing control on ADC sampling and resolver sampling; Step 4.3: The sampling result is calculated by the MDCM module of the application software layer ASW to output the PWM duty cycle, and the dead zone is set to protect the system.

[0016] Furthermore, in step 4.2, the timing control includes the following steps: Step 4.2.1: Different tasks use different clock counters to count at different clock frequencies, and their respective period values ​​are different. For example, for a task with a 100us period at a clock frequency of 100MHz, the period count value is 100us*100MHz=10000, while for a task with a 1ms period, the period count value is 1ms*100MHz=100000, and so on; Different tasks have different clock counter starting points, which are set according to the priority. The starting point of the task with the highest priority P1 is zero and generates a start pulse signal. The starting point of the task with the second highest priority P2 starts after the P1 task is completed, that is, after the first P1 task is completed, a pulse signal of the priority completion mark is output. The P2 task counter starts its own counting from 0 when it detects the completion mark pulse signal of P1, and outputs a completion mark pulse signal after the first P2 task is completed, and so on. Step 4.2.2: The highest priority task starts counting the operation time after receiving the start pulse signal at time zero, where the time consumed by the program operation is fixed and determined during system design. After the operation is completed, the current calculation result is saved and output, and a pulse signal of the completion mark of the module is generated. The end of the movement refers to when the operation time count value reaches the set value; Then, the calculation of the next priority is started according to the same principle, and the calculation of the lower priority is carried out by analogy. At this time, the end signal of the highest priority is the start signal of the next priority, and the end signal of the next priority is the start signal of the lower priority. Step 4.2.3: The calculation output result of the Task is saved at the end of the operation to ensure that the output result at this time is the desired correct result. Because the functional modules in the FPGA structure are always running, each clock will continuously update the calculation result, and thus continuously output the process value. Therefore, the real-time output value cannot be used as the calculation result. Instead, the calculation is started and the correct result is read through the start and end pulse signals.

[0017] Further, in step 4.3, the dead zone setting includes the following steps: Step 4.3.1: According to the duty cycle and PWM period, multiply the two to calculate the pulse width Width; in: PWM cycle: refers to the time from the beginning to the end of a periodic change of the PWM signal; Duty cycle: refers to the proportion of high level time relative to PWM period in a pulse cycle; d*T=Width; Step 4.3.2: Then, taking the center point of the PWM cycle as the midpoint, calculate the comparison values ​​Cmp1 and Cmp2 on both sides; Where: Cmp2-Cmp1=Width; Step 4.3.3: Shift Cmp1 rightward by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the upper tube (i.e. Cmp1+Td / 2). When the counter counts to this value, the output signal is flipped, i.e. the level changes from low level to high level at the moment of H_start. Step 4.3.4: Shift Cmp2 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the upper tube (i.e. Cmp2-Td / 2). When the counter counts to this value, the output signal is flipped, that is, the level changes from high level to low level at the H_end moment; Step 4.3.5: Shift Cmp1 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the lower tube (i.e. Cmp1-Td / 2). When the counter counts to this value, the output signal is flipped, that is, the level changes from high level to low level at the moment of L_end; Step 4.3.6: Shift Cmp2 rightward by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the lower tube (i.e. Cmp2+Td / 2). When the counter counts to this value, the output signal is flipped, i.e. the level changes from low level to high level at the moment of L_start; Realize the generation of center-symmetrical PWM wave and the insertion of dead zone interval.

[0018] Compared with the prior art, the present invention has the following beneficial effects: A method and system for improving motor control performance based on MPSoC technology. The present invention uses the MPSoC chip as the electric drive control body and realizes performance improvement through the PL module in the MPSoC chip, thereby reducing the control cycle and fault protection response time and improving the response efficiency of the electric drive control system.

[0019] A method and system for improving motor control performance based on MPSoC technology implements multi-line parallel computing of multi-tasks and priority tasks through the PL module, thereby achieving effective management of each functional module and each Task, ensuring the stability and correctness of the operating results.

[0020] The present invention provides a method and system for improving motor control performance based on MPSoC technology. By setting the PL module and the PS module, the functional modules are re-divided to achieve optimal utilization of performance and resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the overall framework diagram of the system of the present invention; Figure 2 It is a framework diagram of the MPSoC chip of the present invention; Figure 3 The periodic table of each task of the PL module of the present invention; Figure 4 A flow chart for running the method of the present invention; Figure 5 A sampling calculation flow chart of the method of the present invention; Figure 6 A timing diagram of the method of the present invention; Figure 7 A schematic diagram of generating a PWM waveform with a dead zone according to the present invention; Figure 8 It is a schematic diagram of the operating time of each module of the present invention.

[0022] In the figure: 1. Motor body; 2. MPSoC chip; 21. PL module; 211. Application software layer ASW; 2111. MDCM module; 2112. Task; 2113. Timing module; 212. Basic software layer BSW; 22. PS module; 221. ADC sampling; 222. Resolver module; 223. PWM wave generation; 23. AXI bus; 3. Host computer. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] A technical solution provided by the present invention: like Figures 1 to 3 As shown, the system for improving motor control performance based on MPSoC technology includes a motor body 1, an MPSoC chip 2 and a host computer 3; The MPSoC chip 2 includes a PL module 21 and a PS module 22; the PL module 21 is an FPGA structure, which is a built-in FPGA structure part of the chip, used to implement the electric drive control algorithm. The FPGA structure is a product further developed on the basis of programmable devices such as programmable array logic and general array logic, and is mainly used as a semi-custom circuit in the field of application-specific integrated circuits; The PS module 22 is an MCU structure, which is a micro control unit, and integrates a series of computer peripheral interfaces, storage, processor and clock circuit, and has control, calculation and communication capabilities; the PS module 22 only performs communication functions with the host computer 3 and data storage functions; This system places functions with high real-time requirements, such as the motor control system, in the PL module 21 to improve computing performance, while communication functions with low real-time requirements are placed in the MCU to achieve optimal utilization of performance and resources; The PL module 21 and the PS module 22 are connected through the AXI bus 23 inside the chip and exchange information; the PL module 21 is connected to the motor body 1, and the PS module 22 is connected to the host computer 3; with MPSoC as the core control chip, the interaction with the host computer 3 and the control of the motor body 1 are realized, and then the electric drive control algorithm and fault protection are realized, thereby improving the response time of the electric drive control; The host computer 3 is used to interact with the user. The host computer 3 acts as a bridge between the user and the electric drive control system, transmits the user's instructions to the MPSoC chip 2 for real-time feedback, and provides the data obtained by the electric drive control system for the user's reference, thereby realizing two-way interaction; The PS module 22 uses a built-in ARM R5 chip. The PS module 22 realizes the CAN communication function with the host computer 3 based on the common automobile communication XCP protocol. The PS uses the built-in ARM R5 chip as the MCU structure and realizes the communication function through the common automobile communication XCP protocol. The PS module 22 serves as a connection bridge between the host computer 3 and the PL module 21, realizing the data interaction between the host computer 3 and the PL. The PL module 21 includes an application software layer ASW211 and a basic software layer BSW212; the application software layer ASW211 mainly implements the motor control algorithm and the timing control between the modules; the application software layer ASW211 includes an MDCM module 2111 and a Timing module 2113; the MDCM module 2111 is a motor drive module, which includes signal filtering, fault diagnosis, torque control and current control functions; the MDCM module 2111 is a general motor control algorithm module, and all its functions are implemented by using FPGA to improve computing performance, reduce computing time, and reduce the computing burden of the MCU; the Timing module 2113 is a timing management module for controlling the MDCM module 2111 and the basic software layer BSW212. Since the hardware structure generated by the FPGA structure is calculated in parallel, the asynchronous calculation delay on different paths may cause target data calculation errors, so the designed Timing module 211 3. Perform timing control to ensure the correctness of calculation. When the motor is working, the Timing module 2113 will generate a timing trigger signal and output it to the MDCM module 2111 and each module in the basic software layer BSW212 for use; the MDCM module 2111 is divided into three Tasks 2112, and the Tasks 2112 are divided into different priorities for calculation. The three Tasks 2112 are 100us, 1ms and 10ms respectively, and correspond to the current algorithm module, the voltage algorithm module and the temperature algorithm module in turn; the current algorithm priorities are current signal filtering, current signal fault and current closed-loop control in turn; the voltage algorithm priorities are voltage signal filtering, voltage signal fault and speed signal fault in turn; the temperature algorithm priorities are temperature signal filtering, temperature signal fault and torque control in turn; the Timing module 2113 performs parallel tasks on the three Tasks 2112 or runs the algorithm modules in a single Task 2112 in parallel; The basic software layer BSW212 mainly realizes signal acquisition and PWM output; the basic software layer BSW212 collects data on current, voltage and temperature, and controls the data acquisition sequence through the application software layer ASW211 during the acquisition process, and outputs PWM according to the collected data; the basic software BSW includes ADC sampling 221, a rotary transformer module 222 and a PWM wave generator 223; the ADC sampling 221 samples the three-phase current of the motor, the bus voltage of the electric drive and the temperature of the motor. The ADC sampling 221 triggers the external ADC chip by outputting a sampling trigger signal at a fixed frequency. Data conversion is performed, and then the converted data is read; the resolver module 222 controls the hard decoding chip to obtain the position and speed signals of the motor body 1; the PWM wave generator 223 performs PWM output through the duty cycle duty calculated by the algorithm of the application software layer ASW211, and configures the dead zone interval, and calculates the sampled data through the motor control algorithm to generate a PWM signal. The PWM signal is a digital signal, and its pulse width will change according to the change of the input signal or the control signal; the pulse width is the duration of the high level, and the protection effect of the electric drive control system is improved by configuring the dead zone interval.

[0025] Figure 1 It is the overall framework diagram of the system, the motor body 1 is connected to the MPSoC chip 2, the MPSoC chip 2 is connected to the host computer 3, the host computer 3 interacts with the user, wherein the MPSoC chip 2 is composed of a PS module 22 and a PL module 21, the PS module 22 and the PL module 21 are connected to each other, the PL module 21 is connected to the motor body 1, and the PS module 22 is connected to the host computer 3. The structures in the framework diagram are all bidirectional interactions, and the current is transmitted by powering on the motor body 1, and the current is transmitted to the host computer 3 through the MPSoC chip 2. The user transmits instructions through the host computer 3, and the host computer 3 transmits the instructions to the PS module 22 in the MPSoC chip 2, and the PS module 22 transmits the instructions to the PL module 21, and the PL module 21 runs the corresponding algorithm program according to the instructions, system status and sampled data.

[0026] Figure 2It is a framework diagram of the MPSoC chip 2. The MPSoC chip 2 consists of a PL module 21 and a PS module 22. The PL module 21 and the PS module 22 are connected via an AXI bus 23. The PS module 22 mainly has a communication function. The PS module 22 is divided into an application software layer ASW211 and a basic software layer BSW212. The basic software layer consists of an ADC sampling 221, a resolver module 222 and a PWM wave generation 223. The application software layer ASW211 consists of an MDCM module 2111 and a Timing module 2113. The Timing module 2113 performs timing control on the ADC sampling 221 and the resolver module 222. The MDCM module 2111 performs algorithm calculations on the data collected by the ADC sampling 221 and the resolver module 222 to obtain the operating status of the motor body 1.

[0027] Figure 3 It is a task periodic table of the PL module 21. The PL module 21 performs three-cycle calculation tasks through the MDCM module 2111, namely the current algorithm module, the current algorithm module and the temperature algorithm module, and prioritizes the tasks within a single algorithm module through the Timing module 2113 to ensure real-time response to the motor body 1.

[0028] like Figures 4 to 8 A method is shown, comprising the following steps: Step 1: Power on the motor body, which transmits current to the MPSoC chip. The PS module in the MPSoC chip starts its own program to connect with the host computer to realize the communication function. The PL module loads the program, and the application software layer ASW and the basic software layer BSW are started. The MPSoC chip is reset and initialized. Step 2: The PS module interacts with the host computer, receives instructions from the host computer and passes them to the PL. The user inputs his own instructions through the host computer. After receiving the instructions, the host computer passes them to the PS module through the CAN communication of the car. The PS module passes the instructions to the PL module through the AXI bus. Step 3: The PL module changes state according to the received instruction; Step 4: The PL module runs the corresponding algorithm program according to the instructions, system status and sampled data. The PL module collects data of the motor body, such as voltage, current and temperature, and transmits the collected data to the algorithm program. The PL module also performs real-time detection and fault detection on the current, voltage and temperature of the motor body according to the algorithm program. Step 4 includes the following steps: Step 4.1: The PL module performs ADC sampling and resolver sampling through the basic software layer BSW; The ADC samples the voltage, current and temperature of the motor body, and the resolver module samples the position and speed of the motor; Step 4.2: At the same time, the Timing module in the application software layer ASW performs timing control on ADC sampling and resolver sampling; The hardware structure of the PL module is parallel computing. The asynchronous computing delay on different paths may lead to target data calculation errors. Therefore, timing control is required to ensure the correct operation of each module. In step 4.2, the timing control includes the following steps: Step 4.2.1: Different tasks use different clock counters to count at different clock frequencies, and their respective period values ​​are different. For example, for a task with a 100us period at a clock frequency of 100MHz, the period count value is 100us*100MHz=10000, while for a task with a 1ms period, the period count value is 1ms*100MHz=100000, and so on; Different tasks have different clock counter starting points, which are set according to the priority. The starting point of the task with the highest priority P1 is set as zero and generates a start pulse signal. The starting point of the task with the second highest priority P2 starts after the P1 task is completed, that is, after the first P1 task is completed, a pulse signal of the priority completion mark is output. The P2 task counter starts its own counting from 0 when it detects the completion mark pulse signal of P1, and outputs a completion mark pulse signal after the first P2 task is completed, and so on. Preferably, the starting points of the clock counters of different tasks can also be the same, and the low priority task will use the last operation result of the high priority task. Step 4.2.2: The highest priority task starts counting the operation time after receiving the start pulse signal at time zero, where the time consumed by the program operation is fixed and determined during system design. After the operation is completed, the current calculation result is saved and output, and a pulse signal of the completion mark of the module is generated. The end of the movement refers to when the operation time count value reaches the set value; Then, the calculation of the next priority is started according to the same principle, and the calculation of the lower priority is carried out by analogy. At this time, the end signal of the highest priority is the start signal of the next priority, and the end signal of the next priority is the start signal of the lower priority. Step 4.2.3: The calculation output result of the Task is only saved when the calculation is completed to ensure that the output result at this time is the desired correct result. Because the functional modules in the FPGA structure are always running, each clock will continuously update the calculation result, and thus continuously output the process value. Therefore, the real-time output value cannot be used as the calculation result. Instead, the calculation is started and the correct result is read through the start and end pulse signals; Step 4.3: The sampling result is calculated by the MDCM module of the application software layer ASW to output the PWM duty cycle, and the dead zone is set to protect the system; At the end of high-power motors and inverters, there are H-bridges or 3-phase bridges composed of high-power tubes and IGBT components. The upper and lower half bridges of each bridge must not be turned on at the same time. However, when the high-speed PWM drive signal reaches the control pole of the power component, it often produces a delay effect due to various reasons, causing a half-bridge component to not be turned off when it should be turned off, causing the power component to burn out; the dead zone is to delay for a period of time after the upper half bridge is turned off before turning on the lower half bridge, or delay for a period of time after the lower half bridge is turned off before turning on the upper half bridge, so as to avoid the burning of the power component and play a protective role; In step 4.3, the dead zone setting includes the following steps: Step 4.3.1: According to the duty cycle and PWM period, multiply the two to calculate the pulse width Width; in: PWM cycle: refers to the time from the beginning to the end of a periodic change of the PWM signal; Duty cycle: refers to the proportion of high level time relative to PWM period in a pulse cycle; d*T=Width; Step 4.3.2: Then, taking the center point of the PWM cycle as the midpoint, calculate the comparison values ​​Cmp1 and Cmp2 on both sides; Where: Cmp2-Cmp1=Width; Step 4.3.3: Shift Cmp1 rightward by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the upper tube (i.e. Cmp1+Td / 2). When the counter counts to this value, the output signal is flipped, i.e. the level changes from low level to high level at the moment of H_start. Step 4.3.4: Shift Cmp2 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the upper tube (i.e. Cmp2-Td / 2). When the counter counts to this value, the output signal is flipped, that is, the level changes from high level to low level at the H_end moment; Step 4.3.5: Shift Cmp1 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the lower tube (i.e. Cmp1-Td / 2). When the counter counts to this value, the output signal is flipped, that is, the level changes from high level to low level at the moment of L_end; Step 4.3.6: Shift Cmp2 rightward by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the lower tube (i.e. Cmp2+Td / 2). When the counter counts to this value, the output signal is flipped, i.e. the level changes from low level to high level at the moment of L_start; Realize the generation of center-symmetrical PWM wave and the insertion of dead zone interval; Step 5: If the PL module detects a fault, it will perform fault processing and enter the corresponding system state. The PL module calculates the collected signals to determine the fault problem and transmits the signal to the host computer through the PS module for the user to view; Step 6: If the PS module receives a shutdown command, it sends it to the PL module to make it go through the shutdown process. The PL module turns off the output, the PS module saves the data, and then powers off to stop driving the motor body.

[0029] Figure 4 This is a flow chart of the operation of the method of the present invention. When the system is working, the motor body is first powered on, the PS module in the MPSoC chip starts its own program to connect with the host computer to realize the communication function, the PL module loads the program, and the application software layer ASW and the basic software layer BSW are started; the MPSoC chip is reset and initialized, the PS module in the MPSoC chip receives user instructions through the host computer, and transmits the instructions to the PS module, the PS module performs data collection and algorithm calculation, and performs real-time detection of the current operating status of the motor body. When a motor body fault is detected, the PS module recalculates the current collected data to determine the fault area. When shutdown is required, the PL module receives the shutdown instruction and sends it to the PL to make it go through the shutdown process. The PS module saves the data, the motor body is powered off, and the work is completed.

[0030] Figure 5 The present invention is a sampling calculation flow chart of the method of the present invention. When the PL module receives the instruction, the basic application layer BSW first starts the ADC sampling and the resolver to synchronously collect the voltage, current, temperature position and speed of the motor body. During the collection process, the Timing module performs timing control on the data collection. The collected data is transmitted to the MDCM module for multi-task parallel calculation. Finally, PWM wave generation is performed to generate a pulse waveform. During the PWM wave generation process, the dead zone interval of the circuit is set to ensure the stability of the circuit operation, thereby ensuring the stability of the system.

[0031] Figure 6This is a timing relationship diagram of the method of the present invention. For the motor body control, the first thing to start should be sampling, so as to obtain the sampling values ​​of analog signals such as voltage and current. Therefore, the triggering of ADC and resolver is placed in the front. After both are completed, the calculation and result reading of each module of the control algorithm are started. The high priority is started and read first, and the second priority is started after completion, and so on. The same is true between different tasks.

[0032] Figure 7 This is a schematic diagram of the PWM waveform generation with dead zone of the present invention, which shows the dead zone insertion interval of the upper half bridge and the lower half bridge. The turning point is the switching point between the high level and the low level. The upper half bridge and the lower half bridge are opened by delaying the generation of the dead zone, thereby improving the stability of the system operation.

[0033] Figure 8 This is a schematic diagram of the running time of each module of the present invention. First, it is the ADC sampling and resolver data acquisition time of the basic software layer BSW, then the multi-task parallel and timing control time of the MDCM module of the application software layer ASW, and finally the time for generating PWM wave. The sum of each running time is the total time required for the entire running process.

[0034] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A system for improving motor control performance based on MPSoC technology, characterized by: It includes a motor body (1), an MPSoC chip (2) and a host computer (3); The MPSoC chip (2) comprises a PL module (21) and a PS module (22); The PL module (21) is used as an FPGA structure, and the PS module (22) is used as an MCU structure; The PL module (21) and the PS module (22) are connected via an AXI bus (23) inside the chip and perform information exchange; The PL module (21) is connected to the motor body (1), and the PS module (22) is connected to the host computer (3); The host computer (3) is used to interact with the user.

2. The system according to claim 1, characterized in that: The PS module (22) uses a built-in ARM R5 chip, and the PS module (22) realizes a CAN communication function with a host computer (3) based on a commonly used automobile communication XCP protocol.

3. The system according to claim 1, characterized in that: The PL module (21) includes an application software layer ASW (211) and a basic software layer BSW (212); The application software layer ASW (211) mainly implements the motor control algorithm and the timing control between the modules; The basic software layer BSW (212) mainly implements signal acquisition and PWM output.

4. The system according to claim 3, characterized in that: The application software layer ASW (211) includes an MDCM module (2111) and a Timing module (2113); The MDCM module (2111) is a motor drive module, which includes signal filtering, fault diagnosis, torque control and current control functions; The Timing module (2113) is a timing management module for controlling the MDCM module (2111) and the basic software layer BSW (212).

5. The method according to claim 1, characterized in that: The MDCM module (2111) is divided into three tasks (2112), and the tasks (2112) are divided into different priorities for calculation. The three tasks (2112) are 100us, 1ms and 10ms respectively, and correspond to the current algorithm module, the voltage algorithm module and the temperature algorithm module in turn; The Timing module (2113) performs parallel tasks on the three Tasks (2112) or runs the algorithm modules within a single Task (2112) in parallel.

6. The system according to claim 4, characterized in that: The basic software layer BSW (212) includes ADC sampling (221), a resolver module (222) and PWM wave generation (223); The ADC sampling (221) samples the three-phase current of the motor, the electric drive bus voltage and the motor temperature; The resolver module (222) controls the hard decoding chip to obtain position and speed signals of the motor body (1); The PWM wave generator (223) performs PWM output according to the duty ratio calculated by the algorithm of the application software layer ASW (211), and configures the dead zone interval.

7. A method, applied to the system according to any one of claims 1 to 6 to improve the motor control performance, characterized in that: The following steps are involved: Step 1: Power on the motor body, the PS module in the MPSoC chip starts its own program, and the PL module loads the program; The MPSoC chip is reset and initialized; Step 2: The PS module interacts with the host computer, receives instructions from the host computer and passes them to the PL; Step 3: The PL module changes state according to the received instruction; Step 4: The PL module runs the corresponding algorithm program according to the instructions, system status and sampled data; Step 5: If the PL module detects a fault, it will perform fault processing and enter the corresponding system state; Step 6: If the PS module receives a shutdown command, it sends it to the PL module to execute the shutdown process.

8. The method according to claim 7, characterized in that: Step 4 includes the following steps: Step 4.1: The PL module performs ADC sampling and resolver sampling through the basic software layer BSW; Step 4.2: At the same time, the Timing module in the application software layer ASW performs timing control on ADC sampling and resolver sampling; Step 4.3: The sampling result is calculated by the MDCM module of the application software layer ASW to output the PWM duty cycle, and the dead zone is set to protect the system.

9. The method according to claim 8, characterized in that: In step 4.2, the timing control includes the following steps: Step 4.2.1: Different tasks use different clock counters to count at the clock frequency, and their respective period values ​​are different; Different tasks have different starting points for their clock counters, which are set according to their priorities; Step 4.2.2: The highest priority task inside the task starts counting the operation time after receiving the start pulse signal at time zero, saves and outputs the current calculation result after the operation is completed, and generates a pulse signal of the completion mark of the module; Then, the next priority level calculations are started with the same principle, and so on for the lower priority level calculations; Step 4.2.3: The calculation output result of the Task is saved at the end of the operation.

10. The method according to claim 8, characterized in that: In step 4.3, the dead zone setting includes the following steps: Step 4.3.1: According to the duty cycle and PWM period, multiply the two to calculate the pulse width Width; in: PWM cycle: refers to the time from the beginning to the end of a periodic change of the PWM signal; Duty cycle: refers to the proportion of high level time relative to PWM period in a pulse cycle; d*T=Width; Step 4.3.2: Then, taking the center point of the PWM cycle as the midpoint, calculate the comparison values ​​Cmp1 and Cmp2 on both sides; Where: Cmp2-Cmp1=Width; Step 4.3.3: Shift Cmp1 rightward by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the upper tube (i.e. Cmp1+Td / 2); Step 4.3.4: Shift Cmp2 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the upper tube (i.e. Cmp2-Td / 2); Step 4.3.5: Shift Cmp1 left by half of the dead time Td / 2 to obtain the actual comparison value of the falling edge of the lower tube (i.e. Cmp1-Td / 2); Step 4.3.6: Shift Cmp2 right by half of the dead time Td / 2 to obtain the actual comparison value of the rising edge of the lower tube (i.e., Cmp2+Td / 2).

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