Behavioral modeling methods for clock and data recovery circuit and analog circuits

Abstract

The invention provides a behavioral modeling method for a clock and data recovery circuit. The behavioral modeling method includes steps of 1, dividing a circuit module in the clock and data recovery circuit into a digital circuit module and an analog circuit module; 2, respectively describing the circuit modules by a Verilog language according to the divided circuit modules. The invention further provides a behavioral modeling method for analog circuits. The behavioral modeling methods for the clock and data recovery circuit and the analog circuits have the advantages that the clock and data recovery circuit can be behaviorally modeled by the aid of the Verilog hardware description language, all the analog circuits can be modeled in the corresponding module, problems that the Verilog language does not support analog voltage and current modeling and simulation is difficult are solved, logic verification engineers can verify models in a top-level manner by the aid of digital simulators, and the model verification efficiency is improved.

Description

technical field [0001] The invention relates to the field of electronic circuit design simulation, in particular to a behavior-level modeling method for clock and data recovery circuits (Clock and Data Recovery, CDR) used in optical fiber communication and modern data communication systems. Background technique [0002] The process of social informatization and people's pursuit of obtaining information promote the development of communication technology and industry. Due to its large capacity, long transmission distance, resource saving, anti-interference, anti-radiation and many other advantages, optical fiber communication is being used more and more widely. In optical communication receivers and modern data communication systems, clock and data recovery circuits have always been the "bottleneck" of the system's operating frequency. Therefore, more and more integrated circuit design engineers focus on high-speed, high-performance, low-cost power consumption in the design ...

AI Technical Summary

Problems solved by technology

[0005] However, existing SOCs contain not only digital control logic, but also analog RF circuits

Since the modeling language such as Verilog language does not support the modeling and simulation of analog circuits such as analog voltage and current, it is difficult to model and simulate analog voltage and current, making the modeling efficiency low

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