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Simulation test method of integrated circuits

An integrated circuit, simulation testing technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of affecting the progress of chip design, time-consuming, lack of recovery, etc., to achieve the effect of shortening the simulation time

Active Publication Date: 2012-11-28
SHENZHEN STATE MICRO TECH CO LTD
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing EDA tools do not have the function of restoring the simulation environment in the next simulation after the simulation is interrupted, so each simulation needs to be stimulated by the same vector before the circuit can run to the desired state. As a result, a lot of time was spent, which seriously affected the design progress of the chip.

Method used

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  • Simulation test method of integrated circuits
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  • Simulation test method of integrated circuits

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Embodiment Construction

[0030] Such as figure 1 As shown, the present invention divides the simulation test time into a plurality of simulation sections, saves the data of the simulation site at different time points specified, and then enables the multi-thread simulation program, and each thread recovers the simulation data of a time point to start the simulation test. The original single-threaded simulation process is divided into multiple simulation threads that can be executed in parallel, which greatly reduces the time for re-simulation.

[0031] Such as figure 2 As shown, the realization of the present invention can be divided into the following three stages:

[0032] Phase 1: Data Preparation

[0033] This stage is mainly to generate lists of various data types, and generate verilog tasks for data saving (save) and data restoration (restore) based on these lists. The specific process is as follows:

[0034] (1), read the netlist (netlist) of the integrated circuit through EDA software, acc...

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Abstract

The invention relates to a simulation test method of integrated circuits, which comprises the following steps of: reading in a netlist of the integrated circuits; generating corresponding list files according to data of a register, a latch, an RAM and an ROM; generating a field data preservation task and a field data recovery task according to a verilog hardware description language by the list files; transferring the field data preservation task at different simulation time points to preserve simulation field data at different appointed simulation time points; generating a plurality of mutually independent simulation threads, wherein every simulation thread starts simulation software; transferring the field data recovery task for initializing the integrated circuit which is in simulationcorrespondence with each simulation software into the field data preserved at different simulation time points, and starting up all the simulation threads for simulation verification. The invention greatly shortens the simulation time and improves the simulation efficiency.

Description

technical field [0001] The invention relates to a circuit simulation test method, in particular to a simulation test method which adopts a segmented form to improve the simulation verification speed of an integrated circuit. Background technique [0002] Modern circuit design technology, in addition to directly drawing circuit diagrams, also has a way to directly implement circuits in language. This language is called Hardware Description Language (Hardware Description Language, HDL). With the development of large-scale logic circuits, hardware description languages ​​have been widely used, among which verilog HDL is the most used. [0003] EDA (Electronic Design Automatic) technology uses computer as a tool to complete design files using hardware description language, and automatically complete logic compilation, simplification, segmentation, synthesis and optimization, layout and routing, simulation and other work. The emergence of EDA technology has greatly improved the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 黎嘉勇田浦延李达
Owner SHENZHEN STATE MICRO TECH CO LTD
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