26 results about "Multiplicative Product" patented technology

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

Systems, methods, and quantum circuits for utilizing a joint modular multiplicative inverse operation to perform quantum decryption. First and second private keys are determined by applying first and second series of quantum phase estimation circuits to first and second pluralities of qubits. The private keys are determined further based on public keys and a base point P. The first and second series of quantum phase estimation circuits include application of a joint modular multiplicative inverse circuit on a first qubit of the first plurality of qubits and a second qubit of the second plurality of qubits that calculates a modular multiplicative inverse of a modular product of a first value of the first qubit and a second value of the second qubit. The first and second private keys are stored in a non-transitory computer-readable memory medium.

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

The invention provides an approximate multiplier based on a field programmable gate array (FPGA), which comprises an asymmetric partial product generation module, a signal processing module and a signal processing module, and is characterized in that the asymmetric partial product generation module is used for processing a received N-bit multiplier and a received N-bit multiplicand to generate an asymmetric approximate partial product matrix of which the line number is halved; the single-step compression module is used for compressing the asymmetric approximate partial product matrix into two rows at one time; and the final summing module is used for summing the two rows of compressed data and outputting a final product. Through the collaborative design of asymmetric partial product generation and single-step compression, high-energy-efficiency and low-delay approximate multiplication is realized on an FPGA platform, and the method is suitable for application scenes such as resource-limited edge calculation and the like.

A system having a multiplication circuit having a plurality of multipliers is disclosed. Each of the plurality of multipliers is configured to receive a data value and a weight value to generate a product value in a convolution operation of a machine learning application. The system further includes an accumulator configured to receive the product value from each of the plurality of multipliers and a register bank configured to store an output of the convolution operation. The accumulator is further configured to receive a portion of values stored in the register bank and to combine the received portion of values with the product values to generate combined values. The register bank is further configured to replace the portion of values with the combined values.

A multiplier unit and a method and apparatus for calculating a dot product of floating point values are disclosed. The apparatus includes an array of multiplier units each including integer logic to multiply integer values of corresponding elements of two vectors, exponent logic to add exponent values of corresponding elements of the two vectors to form un-biased exponent values, and a local shifter to form a first shifted value by shifting an integer product value in a predetermined direction by a number of bits based on a difference between the un-biased exponent value corresponding to the integer product value and a maximum un-biased exponent value of the array of multiplier units. An adder tree adds the shifted values output from the local shifters of the array of multiplier units to form an output, and an accumulator accumulates the output of the adder unit.

This invention discloses a method for input independence analysis of large-scale digital circuits based on BDD. The method converts the circuit Verilog file into a NAND graph (AIG) and performs logic optimization to extract the sets of input and output variables. It then converts the AIG network into a global BDD representation and reduces the number of nodes. A multivariate product term cube is constructed with respect to input groups S and X. The Boolean derivative of Di with respect to each input variable in input group S is calculated, and the result is logically ORed to obtain the synthesis sensitivity function diff_or_i. The method then performs the logical inverse operation and full quantization, extracts the specific logical assignment vector of input group L, and determines the independence of Di with respect to input group S. This method avoids the computational bottleneck of exponential complexity and still possesses good computational performance and scalability in large-scale digital circuits. Its independence determination results are unique and reliable, and it can be widely applied in scenarios such as logic synthesis, formal verification, security and testability analysis.

Method for unmapping a modulation symbol comprising: a classification (101) of each bit of the symbol into a first group or a second group; a determination (102) of different pairs, each defining a slope and a y-intercept of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation; for each bit of the first group, a calculation (103) of LLR as a product between a multiplicative factor and a real or imaginary part of the symbol; a verification (104) of inequalities; for each bit of the second group, a calculation (108) of LLR as a function of the real and imaginary parts of the symbol and as a function of parameters selected (107) from subsets of the results obtained for the inequalities (105, 106). Figure for the abstract: Fig. 1

Systems and techniques for implementing an energy-efficient multiplier-accumulator include generating symbols for a product of multiplications based on a corresponding set of multiplicands and multipliers, and generating an offset value based on a number of negative symbols in the generated symbols. Bit-by-bit negation is selectively performed on each product of the multiplications based on the generated symbols, and after performing the selective bit-by-bit negation, each product resulting from the multiplications is summed. The offset value is added to a final result of the summing based on a number of negative symbols in the generated symbols. Prior to the multiplication, one or more of the multiplicand and the multiplier are converted to a signed magnitude representation.

Systems, methods, and quantum circuits for utilizing a joint modular multiplicative inverse operation to perform quantum decryption. First and second private keys are determined by applying first and second series of quantum phase estimation circuits to first and second pluralities of qubits. The private keys are determined further based on public keys and a base point P. The first and second series of quantum phase estimation circuits include application of a joint modular multiplicative inverse circuit on a first qubit of the first plurality of qubits and a second qubit of the second plurality of qubits that calculates a modular multiplicative inverse of a modular product of a first value of the first qubit and a second value of the second qubit. The first and second private keys are stored in a non-transitory computer-readable memory medium.

The application provides a compressor-based FPGA approximate multiplier, and belongs to the field of integrated circuits.The compressor-based FPGA approximate multiplier comprises a partial product generation module, which is used for performing AND operation on each bit of a multiplier and each bit of a multiplicand to generate a partial product matrix; a first accurate compression module, which is used for performing first accurate compression on the partial product matrix based on a plurality of grouping carry compressors to obtain a first compressed element matrix; wherein each grouping carry compressor comprises two LUTs; a second approximate compression module, which is used for performing second approximate compression on the first compressed element matrix by using a plurality of LUTs to obtain a second compressed element matrix; and a carry adder module, which is used for determining a product result by using a carry chain of an FPGA according to the second compressed element matrix.The application improves the utilization rate of an FPGA look-up table and reduces the power consumption of the multiplier.

Systems and methods are provided to perform multiply-accumulate operations of at least one normalized number in a systolic array. The systolic array can obtain a first input and detect that the first input is denormal. Based on determining the first input is denormal, the systolic array can generate a first normalized number by normalizing the first input. Processing elements of the systolic array can include a multiplier and an adder. The multiplier can multiply the first normalized number by a second normal or normalized number to generate a multiplier product and the adder can add an input partial sum to the multiplier product to generate an addition result.

A multiplier device includes a masking circuit that masks a multiplicand and a multiplier based on a random number to obtain a masked multiplicand and a masked multiplier, respectively; a first intermediate arithmetic circuit that obtains a masking term defined based on the masked multiplicand, the masked multiplier, and the random number, and obtains a multiple random number result by multiplication of the random number and the masking term; a second intermediate arithmetic circuit that obtains a partial product result of the masked multiplicand and the masked multiplier and a multiple modulus result of the modulus and the quotient of the modulus; and an accumulation circuit that accumulates the partial product result, the multiple modulus result, and the multiple random number result to an intermediate result of the previous cycle.

An activation function unit can compute an activation function approximated by a Taylor series. An activation function unit may include multiple computational elements. Each computational element may include two multipliers and one accumulator. The first multiplier may compute an intermediate product using an activation, such as the output activation of a DNN layer. The second multiplier may compute terms of a Taylor series approximating the activation function based on the intermediate product from the first multiplier and the coefficients of the Taylor series. The accumulator may compute a partial sum of the terms as the output of the activation function. The number of terms may be determined based on a predetermined precision of the output of the activation function. An activation function unit can handle multiple activations. Different activations may be input to different computational elements in different clock cycles. An activation function unit may compute activation functions with different precisions.

Masked scalar blinding circuits for a side channel analysis (SCA) attack countermeasure are provided. A circuit can include logic gates configured to receive a private key and generate a first private key value and a second private key value that sum to the private key, a first multiplier configured to generate a first product based on a first random number and a multiplicative group order, a second multiplier configured to generate a second product based on a second random number and the multiplicative order group, and circuitry configured to generate a result and a carry out, based on the first private key value, second private key value, the first product, and the second product.

A multiplier apparatus computes multiplication of a multiplicand and a multiplier to give a product. A multiplicand separator and a multiplier separator receive n bit numbers and separate them into high order segments and low order segments. A first multiplier multiplies the high order segments. Second and third multipliers multiply the high order and low order segments. The products of these multiplications are added together by an adder to give a multiplication product. Another implementation uses rounding logic to allow fewer bits in the multipliers. The adder can be a three-way adder or a combination of two-way adders.

A secure selective product computation system (100) has conditions [c0], . . . , [cn−1] and a binary table including m0,0, m0,1, . . . , mn−1,0, and mn−1, 1 as inputs, and outputs a total product [A] of multipliers selected according to the conditions. A condition integrator (11) calculates share values [cici+1]. A table convertor (12) generates a 4-value table including m′00, m′01, m′10, and m′11 A public value multiplier (13) calculates [ai]:=[cici+1](m00+m11−m01−m10)+[ci](mi+1,0−mi,0)+[ci+1](mi,1−mi,0)+mi,0. A real number multiplier (14) calculates a value [A] obtained by multiplying all [ai]. A selective multiplier (15) multiplies [A] by a multiplier selected from multipliers mn−1, 0 and mn−1,1 according to cn−1 when n is an odd number.

The data processing device comprises a product calculation circuit for calculating a first group of products and a second group of products, the first group of products comprising products of high N bits of a first multiplier and a first multiplicand and products of high N bits of a second multiplier and a second multiplicand, and the second group of products comprising products of low N bits of the first multiplier and the first multiplicand of the data processing device and products of low N bits of the second multiplier and the second multiplicand of the data processing device, the first multiplier and the second multiplier are both 2N bits, and N is a positive integer. An accumulation circuit is used for accumulating the first group of products and the second group of products respectively. By merging partial products with the same left shift number in multiple groups of multiplication operations and accumulating the merged results respectively, the logic overhead of the data processing device is reduced.

The invention discloses a novel hybrid precision convolution multiplier-adder, and belongs to the technical field of artificial intelligence chip design and deep learning acceleration. The multiplier and adder supports two core data formats of INT16 and FP16, and efficient sharing of integer and floating point multiplication and addition resources is realized by improving a floating point number operation method. The core of the method is to deform a traditional FP16 floating-point number representation method, so that a 16-bit * 16-bit integer multiplier can be used in the calculation process of the method, and meanwhile, a multi-stage calculation architecture (including modules such as MTS calculation, product and maximum order code solution, symbol processing and shifting, adder tree summation and the like) is adopted, so that delay caused by multiple alignment of order codes is reduced. According to the design, multiplier and adder tree resources are multiplexed, on the premise that the accuracy loss is controllable, hardware resource redundancy and operation complexity are reduced, the advantage of comprehensive performance is more remarkable along with increase of the order number of the multiplier and adder, and the method is suitable for efficient acceleration scenes of deep learning convolution operation.

Method for determining a modular inverse of a number Q modulo a module P, Q and P being prime numbers, P being masked into first parts, the method comprising the determinations of: - (S2) a first and a second non-zero and coprime multiplicative masks, - (S4) another module masked by applying the first multiplicative mask to the module, - (S6) a masked number equal to the product of the second multiplicative mask and the number, - (S10) an intermediate inverse D resulting from a multiplication of a multiplicative inverse of the other masked module by the first multiplicative mask modulo the masked number, - (S12) each second part of a masking of a dividend having a value with N equal to , with the multiplication of D and a third distinct part of the same masking of the module, - (S14) the exact division of the dividend by Q, in masked form. Figure for the abstract: fig. 3.

Disclosed is a method for demapping a modulation symbol, comprising: - classifying (101) each bit of the symbol into a first group or into a second group, - determining (102) N different pairs (αk,βk) each defining a slope and an ordinate at the origin of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation, - for each bit of the first group, calculating (103) an LLR as a product between a multiplicative factor and a real part or an imaginary part of the symbol, - verifying (104) N inequalities αk|Re(s)| + βk ≤ |Im(s)|, - for each bit of the second group, calculating (108) the LLR depending on the real part and imaginary part of the symbol and depending on parameters (107) selected from subsets of the results obtained for the N inequalities (105, 106).

The application relates to a lookup table-based modular multiplier and a modular multiplication method. The modular multiplier comprises a multiplier module, which is used for tripartite decomposition of a multiplier and a multiplicand to obtain a first polynomial of multiplication operation of the multiplier and the multiplicand; quadruple decomposition of the multiplier and the multiplicand of each multiplication operation in the first polynomial to obtain each second polynomial of each multiplication operation in the first polynomial; operation based on each second polynomial to obtain a product of the multiplication operation of the multiplier and the multiplicand; a modulus reduction module connected with the multiplier module, which is used for large-bit-width modulus reduction operation of the product and a modulus to obtain a first calculation result; small-bit-width modulus reduction operation of the first calculation result and the modulus to obtain a modular multiplication result, consumption of hardware resources and complexity of circuit design are reduced, and calculation time delay is effectively reduced.