38 results about "Multiplicative Product" patented technology

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

The invention relates to the technical field of artificial intelligence, in particular to an approximate multiplication method based on Point data and an arithmetic unit, and the method comprises the steps: carrying out the analysis processing of the obtained Point data, carrying out the splicing operation of the exponential expansion bit and the exponent of each piece of Point data, and determining a mantissa truncation bit width control signal according to the equivalent exponent bit of the Point data; two mantissa bits obtained through analysis are converted into logarithm domain tail values, truncation errors are compensated for the truncated logarithm domain tail values, error compensation is carried out on a logarithm domain mantissa product according to a numerical value interval where the logarithm domain tail values are located, and a linear domain equivalent index is processed and split to obtain an exponential expansion bit and an exponential bit of the product; through the design of the novel error compensation circuit, the calculation error is effectively reduced by using relatively low extra overhead, and the energy efficiency and the calculation precision of the Point multiplier are considered.

Systems, methods, and quantum circuits for utilizing a joint modular multiplicative inverse operation to perform quantum decryption. First and second private keys are determined by applying first and second series of quantum phase estimation circuits to first and second pluralities of qubits. The private keys are determined further based on public keys and a base point P. The first and second series of quantum phase estimation circuits include application of a joint modular multiplicative inverse circuit on a first qubit of the first plurality of qubits and a second qubit of the second plurality of qubits that calculates a modular multiplicative inverse of a modular product of a first value of the first qubit and a second value of the second qubit. The first and second private keys are stored in a non-transitory computer-readable memory medium.

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

The embodiment of the invention provides an object detection scheme based on a lookup table, and relates to the technical field of computer vision, and the method comprises the steps: carrying out the unified quantification of weight parameters of convolution kernels of all convolution layers in a pre-trained object detection model and an activation value of a generated feature map; creating a two-dimensional multiplication lookup table; inputting a to-be-detected image into the object detection model, and when a calculation process enters a target convolutional layer, obtaining a feature map corresponding to the to-be-detected image after unified quantization and a convolution kernel in the target convolutional layer after quantization; aiming at each element in the feature map, regarding the element as a first multiplier, and regarding the corresponding element of the element in the convolution kernel as a second multiplier; inputting the first multiplier and the second multiplier into a two-dimensional multiplication lookup table to obtain binary intermediate products, performing shift zero filling on the binary intermediate products, and then performing summation to obtain a target product; and generating a detection tensor based on each obtained target product. Through the object detection method, the detection efficiency of the object in the image can be improved.

The invention provides an approximate multiplier based on a field programmable gate array (FPGA), which comprises an asymmetric partial product generation module, a signal processing module and a signal processing module, and is characterized in that the asymmetric partial product generation module is used for processing a received N-bit multiplier and a received N-bit multiplicand to generate an asymmetric approximate partial product matrix of which the line number is halved; the single-step compression module is used for compressing the asymmetric approximate partial product matrix into two rows at one time; and the final summing module is used for summing the two rows of compressed data and outputting a final product. Through the collaborative design of asymmetric partial product generation and single-step compression, high-energy-efficiency and low-delay approximate multiplication is realized on an FPGA platform, and the method is suitable for application scenes such as resource-limited edge calculation and the like.

Method for determining a modular inverse of a number Q modulo a module P, Q and P being prime numbers, P being masked in first parts, the method comprising the determinations:- (S2) of a first and a second non-zero multiplicative masks which are prime to each other,- (S4) of another masked module by applying the first multiplicative mask to the module,- (S6) of a masked number equal to the product of the second multiplicative mask and the number,- (S10) of an intermediate inverse D resulting from a multiplication of a multiplicative inverse of the other masked module by the first multiplicative mask modulo the masked number,- (S12) of each second part of a masking of a dividend having the value with N equal to , with the multiplication of D and of a third distinct part of the same masking of the module,- (S14) of the exact division of the dividend by Q, in masked form. Figure for the abstract: fig. 3.

The embodiment of the present application provides a data processing method, apparatus, processor, computer equipment, medium and program, wherein the method includes: obtaining data to be processed; determining input data for a modular product operation of an elliptic curve cryptographic algorithm, wherein the input data includes multiple input multipliers; determining the accumulation of multiple product terms corresponding to the multiplication of the binary representations of the multiple input multipliers; using a correction factor of an intermediate domain and a prime number of a prime number domain, in the gradual accumulation process of the accumulation of multiple product terms, correcting the accumulated result of each step to obtain multiple corrected results, and the last corrected result corresponds to the result of the modular product operation of the intermediate domain; wherein the correction factor is used to map the operation to the intermediate domain to eliminate the division operation; mapping the last corrected result back to the prime number domain to obtain the result of the modular product operation in the prime number domain, and determining the data processing result based on the result of the operation. The embodiment of the present application can improve the data processing performance of the elliptic curve cryptographic algorithm.

A system having a multiplication circuit having a plurality of multipliers is disclosed. Each of the plurality of multipliers is configured to receive a data value and a weight value to generate a product value in a convolution operation of a machine learning application. The system further includes an accumulator configured to receive the product value from each of the plurality of multipliers and a register bank configured to store an output of the convolution operation. The accumulator is further configured to receive a portion of values stored in the register bank and to combine the received portion of values with the product values to generate combined values. The register bank is further configured to replace the portion of values with the combined values.

A multiplier unit and a method and apparatus for calculating a dot product of floating point values are disclosed. The apparatus includes an array of multiplier units each including integer logic to multiply integer values of corresponding elements of two vectors, exponent logic to add exponent values of corresponding elements of the two vectors to form un-biased exponent values, and a local shifter to form a first shifted value by shifting an integer product value in a predetermined direction by a number of bits based on a difference between the un-biased exponent value corresponding to the integer product value and a maximum un-biased exponent value of the array of multiplier units. An adder tree adds the shifted values output from the local shifters of the array of multiplier units to form an output, and an accumulator accumulates the output of the adder unit.

This invention discloses a method for input independence analysis of large-scale digital circuits based on BDD. The method converts the circuit Verilog file into a NAND graph (AIG) and performs logic optimization to extract the sets of input and output variables. It then converts the AIG network into a global BDD representation and reduces the number of nodes. A multivariate product term cube is constructed with respect to input groups S and X. The Boolean derivative of Di with respect to each input variable in input group S is calculated, and the result is logically ORed to obtain the synthesis sensitivity function diff_or_i. The method then performs the logical inverse operation and full quantization, extracts the specific logical assignment vector of input group L, and determines the independence of Di with respect to input group S. This method avoids the computational bottleneck of exponential complexity and still possesses good computational performance and scalability in large-scale digital circuits. Its independence determination results are unique and reliable, and it can be widely applied in scenarios such as logic synthesis, formal verification, security and testability analysis.

Method for unmapping a modulation symbol comprising: a classification (101) of each bit of the symbol into a first group or a second group; a determination (102) of different pairs, each defining a slope and a y-intercept of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation; for each bit of the first group, a calculation (103) of LLR as a product between a multiplicative factor and a real or imaginary part of the symbol; a verification (104) of inequalities; for each bit of the second group, a calculation (108) of LLR as a function of the real and imaginary parts of the symbol and as a function of parameters selected (107) from subsets of the results obtained for the inequalities (105, 106). Figure for the abstract: Fig. 1

Examples are disclosed involving obtaining solutions to m-order multi-product formulas to solve quantum computing problems involving product formulas. One example provides a method comprising selecting a set of exponents k j , where each k j is a real number and is an exponent of a linear combination in the form of a product formula. Based on the set of exponents k j , a set of pre-factors a j The determination is based on an underdetermined solution of an mxM linear system of equations, where M is the number of low-order product formulas in the linear combination of the product formulas. The set of indices k j and the set of pre-factors a j is used to solve the quantum computing problem including the product formula. By minimizing the set of exponents k j and the set of pre-factors a j , a sparse solution of the multi-product formula is generated, thereby reducing computation time and scaling.

Systems and techniques for implementing an energy-efficient multiplier-accumulator include generating symbols for a product of multiplications based on a corresponding set of multiplicands and multipliers, and generating an offset value based on a number of negative symbols in the generated symbols. Bit-by-bit negation is selectively performed on each product of the multiplications based on the generated symbols, and after performing the selective bit-by-bit negation, each product resulting from the multiplications is summed. The offset value is added to a final result of the summing based on a number of negative symbols in the generated symbols. Prior to the multiplication, one or more of the multiplicand and the multiplier are converted to a signed magnitude representation.

Systems, methods, and quantum circuits for utilizing a joint modular multiplicative inverse operation to perform quantum decryption. First and second private keys are determined by applying first and second series of quantum phase estimation circuits to first and second pluralities of qubits. The private keys are determined further based on public keys and a base point P. The first and second series of quantum phase estimation circuits include application of a joint modular multiplicative inverse circuit on a first qubit of the first plurality of qubits and a second qubit of the second plurality of qubits that calculates a modular multiplicative inverse of a modular product of a first value of the first qubit and a second value of the second qubit. The first and second private keys are stored in a non-transitory computer-readable memory medium.

The application provides a compressor-based FPGA approximate multiplier, and belongs to the field of integrated circuits.The compressor-based FPGA approximate multiplier comprises a partial product generation module, which is used for performing AND operation on each bit of a multiplier and each bit of a multiplicand to generate a partial product matrix; a first accurate compression module, which is used for performing first accurate compression on the partial product matrix based on a plurality of grouping carry compressors to obtain a first compressed element matrix; wherein each grouping carry compressor comprises two LUTs; a second approximate compression module, which is used for performing second approximate compression on the first compressed element matrix by using a plurality of LUTs to obtain a second compressed element matrix; and a carry adder module, which is used for determining a product result by using a carry chain of an FPGA according to the second compressed element matrix.The application improves the utilization rate of an FPGA look-up table and reduces the power consumption of the multiplier.

A neural network accelerator is disclosed that includes a multiplication unit, an adder-tree unit and an accumulator unit. The multiplication unit and the adder tree unit are configured to perform lattice-multiplication operations. The accumulator unit is coupled to an output of the adder tree to form dot-product values from the lattice-multiplication operations performed by the multiplication unit and the adder tree unit. The multiplication unit includes n multiplier units that perform lattice-multiplication-based operations and output product values. Each multiplier unit includes a plurality of multipliers. Each multiplier unit receives first and second multiplicands that each include a most significant nibble (MSN) and a least significant nibble (LSN). The multipliers in each multiplier unit receive different combinations of the MSNs and the LSNs of the multiplicands. The multiplication unit and the adder can provide mixed-precision dot-product computations.

The invention relates to a modular multiplier based on a lookup table and a modular multiplication operation method, and the modular multiplier comprises a multiplier module which is used for carrying out the three-decomposition of a multiplier and a multiplicand, and obtaining a first polynomial of the multiplication operation of the multiplier and the multiplicand; performing four decomposition on a multiplier and a multiplicand of each multiplication operation in the first polynomial to obtain each second polynomial of each multiplication operation in the first polynomial; performing operation based on each second polynomial to obtain a product of multiplication operation of the multiplier and the multiplicand; the modular reduction module is connected with the multiplier module and is used for carrying out large-bit-width modular reduction operation based on the product and the modulus to obtain a first calculation result; and performing small-bit-width modular reduction operation based on the first calculation result and the modulus to obtain a modular multiplication result, thereby reducing the consumption of hardware resources and the complexity of circuit design, and effectively reducing the calculation time delay.

Systems and methods are provided to perform multiply-accumulate operations of at least one normalized number in a systolic array. The systolic array can obtain a first input and detect that the first input is denormal. Based on determining the first input is denormal, the systolic array can generate a first normalized number by normalizing the first input. Processing elements of the systolic array can include a multiplier and an adder. The multiplier can multiply the first normalized number by a second normal or normalized number to generate a multiplier product and the adder can add an input partial sum to the multiplier product to generate an addition result.

A multiplier circuit for multiplying two numbers in which at least one number is represented by two binary strings, proposed to be called "substrings". The combined value of the substrings is the represented number. This allows many combinations of different pairs of substrings to represent the same value. The multiplier circuit expands the numbers into partial products that are each in the form of two binary strings. The partial products are added up after treatments select a pair of binary strings to represent each partial product, so that the partial products add up without any carry-overs. Thus, here is no propagation delay and the multiplication product can be speedily calculated.

The present disclosure relates to arbitrary coefficient multiplier-free FIR filters in the Hough form and provides embodiments of filters suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes an arrangement of series connections of unit delays and summers in an alternating pattern. The filter circuit also includes a plurality of coefficient multipliers, each coefficient multiplier having a respective output connected to one or more of the summers, and each coefficient multiplier includes a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to a multiplexing stage of the plurality of coefficient multipliers.

A multiplier device includes a masking circuit that masks a multiplicand and a multiplier based on a random number to obtain a masked multiplicand and a masked multiplier, respectively; a first intermediate arithmetic circuit that obtains a masking term defined based on the masked multiplicand, the masked multiplier, and the random number, and obtains a multiple random number result by multiplication of the random number and the masking term; a second intermediate arithmetic circuit that obtains a partial product result of the masked multiplicand and the masked multiplier and a multiple modulus result of the modulus and the quotient of the modulus; and an accumulation circuit that accumulates the partial product result, the multiple modulus result, and the multiple random number result to an intermediate result of the previous cycle.

An activation function unit can compute an activation function approximated by a Taylor series. An activation function unit may include multiple computational elements. Each computational element may include two multipliers and one accumulator. The first multiplier may compute an intermediate product using an activation, such as the output activation of a DNN layer. The second multiplier may compute terms of a Taylor series approximating the activation function based on the intermediate product from the first multiplier and the coefficients of the Taylor series. The accumulator may compute a partial sum of the terms as the output of the activation function. The number of terms may be determined based on a predetermined precision of the output of the activation function. An activation function unit can handle multiple activations. Different activations may be input to different computational elements in different clock cycles. An activation function unit may compute activation functions with different precisions.

Masked scalar blinding circuits for a side channel analysis (SCA) attack countermeasure are provided. A circuit can include logic gates configured to receive a private key and generate a first private key value and a second private key value that sum to the private key, a first multiplier configured to generate a first product based on a first random number and a multiplicative group order, a second multiplier configured to generate a second product based on a second random number and the multiplicative order group, and circuitry configured to generate a result and a carry out, based on the first private key value, second private key value, the first product, and the second product.

Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided for calculating a plurality of powers of the common value, processing each of a plurality of pairs of first and second elements of the input values, wherein the processing comprises multiplying the first elements of the input values by the common value and combining the products with second elements of the input values, performing additional processing using the plurality of processed pairs as the subsequent set of input values and using a power of the common value, multiplying each of the processed pairs with one of the plurality of powers of the common value to generate a set of output values, accumulating the set of output values, and providing the digest as a function of the set of output values.

A multiplier apparatus computes multiplication of a multiplicand and a multiplier to give a product. A multiplicand separator and a multiplier separator receive n bit numbers and separate them into high order segments and low order segments. A first multiplier multiplies the high order segments. Second and third multipliers multiply the high order and low order segments. The products of these multiplications are added together by an adder to give a multiplication product. Another implementation uses rounding logic to allow fewer bits in the multipliers. The adder can be a three-way adder or a combination of two-way adders.