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High-performance approximate multiplier based on operand cutting and calculation method thereof

A technology of operands and multipliers, applied in high-performance multipliers and computing fields, can solve problems such as power supply limitations, large consumption, and outstanding power consumption of image processing units, and achieve the effect of shortening delays

Pending Publication Date: 2022-07-01
HEFEI UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The image filtering operation needs to consume a large number of multiplication and addition operation units, and the accuracy requirements for the results in the filtering process are not very strict
If the precise multiplier is used, the calculation unit will be too large, and the multiplier flips frequently, which makes the power consumption of the image processing unit prominent.
At the same time, because most of the terminals of edge computing are mobile devices, their power supply is limited, and the power consumption of the devices is particularly prominent.

Method used

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  • High-performance approximate multiplier based on operand cutting and calculation method thereof
  • High-performance approximate multiplier based on operand cutting and calculation method thereof
  • High-performance approximate multiplier based on operand cutting and calculation method thereof

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Embodiment Construction

[0068] In this embodiment, as figure 1 As shown in the figure, a high-performance approximate multiplier based on operand clipping is mainly used in image processing, deep learning and other fault-tolerant application fields and to deal with battery life challenges in extreme environments, and specifically includes: partial product generation module, partial product Compression module, carry adder module and shift module;

[0069] The partial product generation module is composed of an operand clipping module and a bit product module; the operand clipping module sets the interception interval k according to the number of digits n of the operand A, and generates an approximate flag bit Ac; Shifting is performed, and then cropping is performed according to the interception interval k, thereby generating an approximate operand Ap; the operand cropping module also processes the operand B to obtain an approximate operand Bp;

[0070] The bit product module uses the AND gate array ...

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Abstract

The invention discloses a high-performance approximate multiplier based on operand cutting and a calculation method of the high-performance approximate multiplier. The approximate multiplier comprises a partial product generation module, a partial product tree compression module, a carry adder module and a shifting module. The partial product generation module comprises an operand cutting module and a bit product module, the operand cutting module performs cutting operation on a multiplier and a multiplicand to obtain an approximate operand, and the bit product module obtains a corresponding partial product; the partial product tree compression module is used for obtaining two final summed addend numbers; the carry adder module is used for finally adding two adders, and the shifting module is used for shifting the output of the carry adder module to obtain a solved binary result. According to the invention, the area, the delay and the power consumption of the multi-bit multiplier can be greatly reduced, and meanwhile, better accuracy can be kept.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to a high-performance multiplier based on operand trimming and a calculation method. Background technique [0002] In recent years, with the rapid development of big data, the image information that needs to be processed increases exponentially. Basic image processing includes image filtering, image edge detection and sharpening. The image filtering operation needs to consume a large number of multiplying and adding operation units, and the precision of the result is not very strict in the filtering process. If an accurate multiplier is used, the calculation unit will be too large, and the multiplier will be flipped frequently, making the power consumption problem of the image processing unit prominent. At the same time, since most of the edge computing terminals are mobile devices, their power supply is limited, and the problem of device power consumption is particular...

Claims

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Application Information

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IPC IPC(8): G06F7/523
CPCG06F7/523
Inventor 杜嘉程王琦王超贾忱皓林木森崔丰麒黄楚盛李明轩吴共庆杜高明孙晓
Owner HEFEI UNIV OF TECH
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