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Approximate multiplier design method based on optimal compensation and approximate multiplier

A design method and technology of multipliers, which are applied in CAD circuit design, instruments, calculations, etc., can solve the problems of low accuracy of results and low accuracy of calculation results of approximate multipliers.

Pending Publication Date: 2020-09-22
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

General approximate multiplication calculations focus on approximate logic calculations for low-weight partial products, while maintaining accurate accumulation of high-weight partial products. Low, so the accuracy of the calculation result of the approximate multiplier is low

Method used

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  • Approximate multiplier design method based on optimal compensation and approximate multiplier
  • Approximate multiplier design method based on optimal compensation and approximate multiplier
  • Approximate multiplier design method based on optimal compensation and approximate multiplier

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Embodiment Construction

[0029] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0030] Compared with the traditional approximate multiplier design method realized by truncating and discarding low-weight column values ​​in the process of part of the multiplication and accumulation process, this application analyzes and processes the values ​​of the discarded columns, and compensates the partial multiplication and accumulation results of high-weight bits.

[0031] In one embodiment, such as figure 1 As shown, an approximate multiplier design method based on optimal compensation is provided, including the following steps:

[0032] Step 102: Design a dis...

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Abstract

The invention relates to an approximate multiplier design method based on optimal compensation and an approximate multiplier. The method comprises the following steps: designing a discarding circuit according to a preset discarding column number k, dividing k columns starting from an LSB bit in a partial multiplication accumulation process of a multiplier into discarding columns, and taking othercolumns as accurate accumulation columns; and designing an error compensation circuit according to a preset compensation digit M, and calculating an average value of the abandoned columns of the M bits as an error compensation value according to the number n1 of the logic values 1 in the highest weight column of the abandoned columns and the probability that the logic value of each bit in the abandoned columns is 1; and calculating a final product by using an accurate accumulation circuit according to the accurate accumulation column and the error compensation value to form an approximate multiplier. By adopting the method, the final product result of the approximate multiplier has the minimum mean square error, and the calculation precision of the approximate multiplier is ensured.

Description

technical field [0001] The present application relates to the technical field of low power consumption digital signal processing circuit design, in particular to an approximate multiplier design method based on optimal compensation and an approximate multiplier. Background technique [0002] In some fault-tolerant applications, the accuracy of calculated values ​​can be moderately reduced, and calculations are performed on an "approximate" basis, and related technologies are collectively referred to as approximate calculations. The main idea of ​​circuit design for approximate computing is to change the logic of circuit implementation and reduce the resources occupied by the circuit by simplifying the circuit structure. Approximate calculation circuits have been widely used in digital signal processing (DSP) systems, multimedia, fuzzy logic and neural networks. While providing practical calculation results for related applications, the circuit is simplified and the chip area...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/30G06F7/523
CPCG06F30/30G06F7/523
Inventor 杨志玺杨俊杨道宁吴先宇李献斌刘思力
Owner NAT UNIV OF DEFENSE TECH
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