Base-16 fixed point divider based on carry-save adder

Abstract

The invention discloses a base-16 fixed point divider based on a carry-save adder and belongs to the technical field of computer digital. The base-16 fixed point divider based on the carry-save adder comprises a detecting-relocating module, a quotient loop generating module, a quotient conversion module, a quotient / remainder adjusting module and an execution control module. According to the base-16 fixed point divider based on the carry-save adder, data is received and regularized through the detecting-relocating module and shifts leftwards. The received regularized data is used for loop operation, and loop iteration generates redundant data. The redundant form quotient value generated by the quotient loop generating module is received. Standard binary complementary form is converted by adoption of the carry-save form. Symbol same sign adjustment is conducted on the quotient result and the remainder result according to the RNS algorithm, and the quotient is adjusted. Finally, corresponding figure is shift rightward after the operation is realized, the result is input in a counter, and the loop execution times are calculated. The path delay of the one-bit generated by the base-16 fixed point divider based on the carry-save adder can be greatly shortened, one time of loop operation can generate four-bit quotient value due to the simple configuration of the divider, and the operating efficiency is improved.

Description

technical field [0001] The invention discloses a radix-16 fixed-point divider, which belongs to the technical field of computer numbers, in particular to a radix-16 fixed-point divider based on a carry-save adder. Background technique [0002] In digital signal processing, communication, image and video processing, the work of dealing with quotient and remainder is often involved, but in general-purpose CPUs and DSPs, dividers are often not specially set up to complete the above work, because division operations are in general programs. The proportion is very small, but it is much more complicated in design than other computing components, so the usual practice is to write instructions on the basis of other computing components, such as ALU and multiplier, to realize the subroutine of division operation. However, in some specific algorithms, such as modulo calculation, numerical conversion, data unpacking algorithm, etc., the division operation occupies a considerable propor...

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Problems solved by technology

However, in some specific algorithms, such as modulo calculation, numerical conversion, data unpacking algorithm, etc., the division operation occupies a considerable proportion, which is the key to improving the performance of the program. It is necessary to set up a special divider. However, the current division operation mainly There are two ways, the first is to design a special high-speed division operation part, which requires multiple devices such as multiple generators, comparators, adder and subtractors, etc. The circuit is quite complicated and the chip area resource is sacrificed to improve the processing speed. It is generally used for high performance. Processor, such as Intel's 45nm Penryn processor; the second is to use existing instructions to implement corresponding division operations, such as converting division operations into subtraction and shift operations, using adders, comparators, and shift adders to complete the division operation

However, this type of method can only obtain a quotient value after each shift and subtraction operation. If the dividend is N bits, it needs to perform N operations to obtain the quotient. The disadvantage is that the operation cycle is long and the performance improvement is not obvious.

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