Shared integer, floating point, polynomial, and vector multiplier

a vector multiplier and floating point technology, applied in the field of multipliers, can solve the problems of large number of multipliers used by processors, large amount of die space consumed by processors, and limited availability of die space on processors
US20130138711A1Active Publication Date: 2013-05-30APPLE INC
9 Cites 30 Cited by

Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
APPLE INC
Publication Date
2013-05-30

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.
Need to check novelty before this filing date? Find Prior Art

Description

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates generally to multipliers, and in particular to methods and mechanisms for performing numerous types of multiplication with the same multiplier circuitry.

[0003] 2. Description of the Related Art

[0004] Modern-day processors often need to perform several different types of multiplication (e.g., integer, floating point, vector, polynomial). The multipliers used by processors are typically large, resource intensive circuits. Implementing numerous separate multipliers to perform each type of multiplication can consume a large amount of die space. Die space on a processor is limited in availability and typically there is only so much die space on the processor available for multiplier circuits. The less space taken up by the multipliers, the more space is available for other circuits, and therefore the number and size of the multipliers should be reduced as much as possible.SUMMARY

[0005] In one embodiment, a shared m...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More