Shared integer, floating point, polynomial, and vector multiplier

a vector multiplier and floating point technology, applied in the field of multipliers, can solve the problems of large number of multipliers used by processors, large amount of die space consumed by processors, and limited availability of die space on processors

Active Publication Date: 2013-05-30
APPLE INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]The encoder output values may be coupled to a plurality of multiplexers. Each multiplexer may select from a plurality of partial products, and the selection may be based on a respective encoder output value. The partial products may be generated from the multiplicand operand and may represent various multiples (e.g., 1×, −1×, 2×, −2×, polynomial 3×, 0) of the multiplicand operand.

Problems solved by technology

The multipliers used by processors are typically large, resource intensive circuits.
Implementing numerous separate multipliers to perform each type of multiplication can consume

Method used

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  • Shared integer, floating point, polynomial, and vector multiplier
  • Shared integer, floating point, polynomial, and vector multiplier
  • Shared integer, floating point, polynomial, and vector multiplier

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Embodiment Construction

[0022]In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one having ordinary skill in the art should recognize that the various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements.

[0023]This specification includes references to “one embodiment”. The appearance of the phrase “in one embodiment” in different contexts does not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any ...

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Abstract

A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention relates generally to multipliers, and in particular to methods and mechanisms for performing numerous types of multiplication with the same multiplier circuitry.[0003]2. Description of the Related Art[0004]Modern-day processors often need to perform several different types of multiplication (e.g., integer, floating point, vector, polynomial). The multipliers used by processors are typically large, resource intensive circuits. Implementing numerous separate multipliers to perform each type of multiplication can consume a large amount of die space. Die space on a processor is limited in availability and typically there is only so much die space on the processor available for multiplier circuits. The less space taken up by the multipliers, the more space is available for other circuits, and therefore the number and size of the multipliers should be reduced as much as possible.SUMMARY[0005]In one embodiment, a shared m...

Claims

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Application Information

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IPC IPC(8): G06F7/487G06F7/523
CPCG06F2207/3812G06F7/5338G06F7/722G06F7/724
Inventor SUGISAWA, JUNJI
Owner APPLE INC
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