High-speed radix-16 Montgomery modular multiplier VLSI (very large scale integrated circuit)

Abstract

The invention discloses a high-speed radix-16 Montgomery modular multiplier VLSI (very large scale integrated circuit) which comprises N-numbered MMCell arithmetic elements, an FIFO (first in first out) storage unit and an alternative data selection unit. The high-speed radix-16 Montgomery modular multiplier VLSI overcomes the defects of low average behavior, low clock frequency, large hardware expenditure, poor practicability and the like in the prior art, thus achieving the advantages of high average behavior, high clock frequency, small hardware expenditure and good practicability.

Description

technical field [0001] This invention relates to electronic circuits and, in particular, to radix-16 high speed Montgomery modular multipliers very large scale integration (VLSI). Background technique [0002] At present, the rapid development of the Internet makes information security technology particularly important, such as online shopping, online banking, data downloading, etc., all need an identity authentication system. In modern cryptography, public key cryptosystem is used to accomplish this task, which can provide a series of security guarantees such as digital signature, identity authentication, data integrity and non-repudiation. [0003] In the public key cryptosystem, the most widely used is the RSA cryptographic algorithm (RSA cryptographic algorithm is an asymmetric cryptographic algorithm). The RSA encryption algorithm is simple and effective, but it is very time-consuming, because the basic operation of RSA is exponentiation operation, and its operand leng...

AI Technical Summary

Problems solved by technology

Firstly, the basis used is not reasonable enough; secondly, the structure of the MM Cell operation unit has not been optimized. figure 2 It can be found in the critical path ( figure 2 Indicated by a longer thick black line) is still very long, and the hardware overhead is relatively large; finally, in the FIFO design, in order to store temporary data SS’ and SC’, two storage units (such as figure 1 ), increasing memory overhead

[0051] To sum up, in the process of realizing the present invention, the inventor found that there are at least defects such as low average performance, low clock frequency, large hardware overhead and poor practicability in the prior art

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