The present invention facilitates
automation of
system on a
chip (SoC) design, manufacture and
verification in a convenient and efficient manner. In one embodiment, a SoC
netlist builder and
verification computer
system of the present invention includes a
user interface module, a parameter
application module, an
expert system module and a
chip level
netlist generation module. The
user interface module provides
user friendly and convenient interfaces that facilitate easy entry and modification of user selections and parameters. The parameter
application module interprets information supplied by the user module and the
expert system module and creates directions (e.g., command lines) passed to other modules for execution. The
expert system module analyzes information and automatically provides SoC building and
verification data including automated addition of default architectural features, automated
insertion of default parameters, and automated input of information to the verification module. The
chip level
netlist generation module automatically generates a chip level netlist, including the instantiation of internal
IC devices and connections between the circuit blocks for internal signals. The verification module automatically generates a
test bench and a logical verification environment including
simulation models (e.g., a chip model and a
system level model).