Encapsulated antenna and manufacturing method thereof

Abstract

A method for manufacturing an encapsulated antenna is provided. The encapsulated antenna includes an antenna structure including an antenna radiation patch, an antenna substrate dielectric layer and areflective ground plane arranged in sequence. The antenna substrate dielectric layer has a first surface and a second surface opposite to each other. The antenna radiation patch is fixed on the firstsurface and the reflective ground plane is fixed on the second surface. Chip; A package having opposite first and second faces, the front face and reflective ground plane of the chip being exposed toand flush with the second face; A rewiring layer comprising an RDL dielectric layer and an RDL metal layer, the RDL metal layer comprising a feeder, a plurality of fan-out leads and a plurality of pads, at least a portion of the pads being connected to the chip through vias in the RDL dielectric layer; And a solder ball implanted on the pad. The encapsulated antenna can reduce its own parasitic parameters while improving antenna radiation patch performance.

Description

technical field [0001] The present disclosure relates to the technical field of packaged antennas, and in particular, to a packaged antenna and a method for manufacturing the packaged antenna. Background technique [0002] With the development of science and technology in recent decades, millimeter waves have gradually developed towards civilian miniaturization and multi-function, and have been widely used in automotive radar, high-speed data communication, industrial automation sensors, and medical equipment. Antenna is an important part in a wireless system, there are two forms of separation and integration. The integrated antenna includes two types: Antenna-on-Chip ("AoC" for short) and Antenna-in-Package ("AiP" for short). The antenna-on-chip technology integrates the antenna and other circuits on the same chip through semiconductor materials and processes. The advantages are high integration, no additional interconnection, and small parasitic effects, especially for th...

AI Technical Summary

Problems solved by technology

For millimeter-wave chip AiP packaging, the traditional packaging technology is to fan out the MMIC chip and integrate it into the AiP system, but this will increase the parasitic parameters of the interconnection

[0008] In addition, many manufacturers currently provide fan-out packaging technology, such as Infineon's eWLB (embedded Wafer Level Ball gridarray, embedded wafer-level ball grid array packaging), TSMC's InFO-WLP, etc., but do not provide Craft customization service

Taking the eWLB process as an example, the package structure manufactured by the eWLB process has only one RDL rewiring layer. When implementing AiP, if the RDL metal layer is used to form the antenna pattern, it is impossible to make a reflective ground plane on the eWLB package, and only a PCB can be used. (Printed Circuit Board, printed circuit board) The wiring layer on the ground plane needs to carefully optimize the PCB structure to cooperate with the antenna design, which brings trouble to the application and increases the application cost

Images