178 results about "Magnetoresistive random-access memory" patented technology

A magnetoresistive random access memory (MRAM) includes a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. A bottom electrode is centrally disposed to be located within a periphery of the MTJ. The bottom electrode has sloped sidewalls that slope inwardly to connect to the MTJ.

A magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction and a spin-orbit torque material. The spin-orbit torque material produces spin polarization along one or more axes based on a current applied to the spin-orbit torque material. A magnetoresistive random access memory (MRAM) device includes an in-plane magnetic tunnel junction and a spin-orbit torque material, where the MRAM device is field-free switching between a parallel state and an anti-parallel state based on a current applied to the spin-orbit torque material.

A magnetoresistive random access memory (MRAM) structure is provided. The MRAM structure includes a chiral spin-orbit torque (SOT) metal bottom electrode (18) underneath a magnetic free layer (26), wherein the chiral SOT metal bottom electrode (18) is surrounded by a via dielectric material structure (24). The chiral SOT metal bottom electrode (18) is such that the charging current direction, the spin current direction, and the spin polarization direction are in the same direction perpendicular to the horizontal surface of the chiral SOT metal bottom electrode (18).

A magnetoresistive random access memory (MRAM) structure is provided. The MRAM structure includes a chiral spin-orbit-torque (SOT) metal bottom electrode (18) under the magnetic free layer (26) where

In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

A method for fabricating a physically unclonable function (PUF) device includes the steps of firs providing a substrate comprising a magnetoresistive random access memory (MRAM) region, a PUF cell region, and a non-PUF cell region, forming a first metal interconnection on the MRAM region, forming a second metal interconnection on the PUF cell region, and forming a third metal interconnection on the non-PUF cell region. Preferably, the first metal interconnection and the second metal interconnection include patterns of different shapes and the first metal interconnection and the third metal interconnection include patterns of same shape.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, and then forming a first cap layer adjacent to the MTJ. Preferably, the first cap layer has a first thickness and a second thickness.

Embodiments for a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device are disclosed. A three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write word line (WWL). In addition, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Likewise, the second type FET includes a read gate in electrical contact with a read word line (RWL). Additionally, the first type FET is disposed over the second type FET. In addition, the three-terminal SOT MRAM device provides a density of three contact polycrystalline pitches (CPPs) per two cells.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

The invention provides a magnetoresistive random access memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a magnetic tunnel junction film layer on the substrate; forming a first dielectric layer on the magnetic tunnel junction film layer; etching the two ends of the first dielectric layer in the first direction so as to enable the two opposite ends of the magnetic tunnel junction film layer in the first direction to extend out of the etched first dielectric layer; forming a metal layer on the magnetic tunnel junction film layer, wherein the metal layer wraps the etched first dielectric layer; and etching the metal layer to form top electrodes on two opposite sides of the first dielectric layer along the first direction. According to the invention, the yield of the MRAM can be improved.

The invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed on the first array region, a first upper electrode disposed on the first MTJ, a second MTJ disposed on the second array region, and a second upper electrode disposed on the second MTJ, wherein the first upper electrode and the second upper electrode comprise different nitrogen-to-carbon ratios.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly, forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a third covering layer beside the MTJ. An ion implantation process is then performed to form a first doped region in the SOT layer and on one side of the MTJ and a second doped region in the SOT layer and on the other side of the MTJ, wherein the first doped region and the second doped region form a ring around the MTJ in a plan view.

A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.

This document discloses a three-dimensional (3D) magnetoresistive random access memory (MRAM) device comprising a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to the main surface of a substrate of the 3D MRAM device. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer among the plurality of insulating layers. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type, the second interconnect structure being configured to interface with the MTJ structure of the cell. The orientation of the first interconnect structure is orthogonal to the second interconnect structure of each of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, and then forming a second cap layer adjacent to the first cap layer. Preferably, a thickness of the first cap layer is greater than a thickness of the second cap layer.

A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.

A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input / output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

A spin-orbit torque magnetoresistive random access memory (SOT MRAM) device is provided. Each SOT MRAM device uses a topological conductor (i.e., a topological metal or a topological semimetal) as both an interconnect layer and an SOT layer, which are integrated at the same metal layer. The SOT MRAM device also includes a magnetic tunnel junction (MTJ) structure contacting the SOT layer, and a contact structure contacting the MTJ structure.

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device primarily includes a magnetoresistive random access memory (MRAM) region and a logic region defined on a substrate. A first metal interconnect is disposed in the MRAM region, and a second metal interconnect is disposed in the logic region. A stop layer extends from the first metal interconnect to the second metal interconnect, and the stop layer on the first metal interconnect and the stop layer on the second metal interconnect have different thicknesses. A magnetic tunneling junction (MTJ) is disposed on the first metal interconnect.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, forming a first oxide layer on the first cap layer, and forming a second cap layer on sidewalls of the first oxide layer. Preferably, a top surface of the second cap layer is higher than a top surface of the MTJ.

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

A patterned magnetoresistive random access memory (MRAM) stack is formed by etching through a plurality of MRAM layers disposed on a substrate by performing a main etch, wherein the main etch includes using ion beam etch (IBE). After the main etch, a gap-fill dielectric material is deposited into the spaces between the patterned MRAM stacks, and the gap-fill dielectric material is selectively etched or otherwise formed to an etch depth above the underlying depth. After forming the gap-fill dielectric material, at least some of the gap-fill dielectric material and any conductive material deposited on sidewalls of the patterned MRAM stack are removed by performing an IBE trim etch.

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.

The utility model relates to a probability bit structure and a magnetic tunnel junction structure. The probabilistic bit structure includes: a transistor; a magnetic tunnel junction (MTJ) operably connected with the transistor through a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA. In one case, a probabilistic bit includes an MTJ structure including: an MTJ cell including an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ cell; the BEVA is connected to the MTJ unit; and a heater disposed between a first intermetallic dielectric (IMD) region and the TEVA. The heater heats the MTJ structure when a voltage or a current is applied to the metallization layer first and second contacts, and the heater is shaped to one of a square, a rectangle, a circle, and an ellipse.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the thickness of the first covering layer is greater than that of the second covering layer;

A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N / Ti) ratios.