124 results about "Magnetoresistive random-access memory" patented technology

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, and then forming a first cap layer adjacent to the MTJ. Preferably, the first cap layer has a first thickness and a second thickness.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

The invention provides a magnetoresistive random access memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a magnetic tunnel junction film layer on the substrate; forming a first dielectric layer on the magnetic tunnel junction film layer; etching the two ends of the first dielectric layer in the first direction so as to enable the two opposite ends of the magnetic tunnel junction film layer in the first direction to extend out of the etched first dielectric layer; forming a metal layer on the magnetic tunnel junction film layer, wherein the metal layer wraps the etched first dielectric layer; and etching the metal layer to form top electrodes on two opposite sides of the first dielectric layer along the first direction. According to the invention, the yield of the MRAM can be improved.

The invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed on the first array region, a first upper electrode disposed on the first MTJ, a second MTJ disposed on the second array region, and a second upper electrode disposed on the second MTJ, wherein the first upper electrode and the second upper electrode comprise different nitrogen-to-carbon ratios.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly, forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a third covering layer beside the MTJ. An ion implantation process is then performed to form a first doped region in the SOT layer and on one side of the MTJ and a second doped region in the SOT layer and on the other side of the MTJ, wherein the first doped region and the second doped region form a ring around the MTJ in a plan view.

This document discloses a three-dimensional (3D) magnetoresistive random access memory (MRAM) device comprising a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to the main surface of a substrate of the 3D MRAM device. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer among the plurality of insulating layers. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type, the second interconnect structure being configured to interface with the MTJ structure of the cell. The orientation of the first interconnect structure is orthogonal to the second interconnect structure of each of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, and then forming a second cap layer adjacent to the first cap layer. Preferably, a thickness of the first cap layer is greater than a thickness of the second cap layer.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.

A spin-orbit torque magnetoresistive random access memory (SOT MRAM) device is provided. Each SOT MRAM device uses a topological conductor (i.e., a topological metal or a topological semimetal) as both an interconnect layer and an SOT layer, which are integrated at the same metal layer. The SOT MRAM device also includes a magnetic tunnel junction (MTJ) structure contacting the SOT layer, and a contact structure contacting the MTJ structure.

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device primarily includes a magnetoresistive random access memory (MRAM) region and a logic region defined on a substrate. A first metal interconnect is disposed in the MRAM region, and a second metal interconnect is disposed in the logic region. A stop layer extends from the first metal interconnect to the second metal interconnect, and the stop layer on the first metal interconnect and the stop layer on the second metal interconnect have different thicknesses. A magnetic tunneling junction (MTJ) is disposed on the first metal interconnect.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, forming a first oxide layer on the first cap layer, and forming a second cap layer on sidewalls of the first oxide layer. Preferably, a top surface of the second cap layer is higher than a top surface of the MTJ.

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

A patterned magnetoresistive random access memory (MRAM) stack is formed by etching through a plurality of MRAM layers disposed on a substrate by performing a main etch, wherein the main etch includes using ion beam etch (IBE). After the main etch, a gap-fill dielectric material is deposited into the spaces between the patterned MRAM stacks, and the gap-fill dielectric material is selectively etched or otherwise formed to an etch depth above the underlying depth. After forming the gap-fill dielectric material, at least some of the gap-fill dielectric material and any conductive material deposited on sidewalls of the patterned MRAM stack are removed by performing an IBE trim etch.

The utility model relates to a probability bit structure and a magnetic tunnel junction structure. The probabilistic bit structure includes: a transistor; a magnetic tunnel junction (MTJ) operably connected with the transistor through a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA. In one case, a probabilistic bit includes an MTJ structure including: an MTJ cell including an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ cell; the BEVA is connected to the MTJ unit; and a heater disposed between a first intermetallic dielectric (IMD) region and the TEVA. The heater heats the MTJ structure when a voltage or a current is applied to the metallization layer first and second contacts, and the heater is shaped to one of a square, a rectangle, a circle, and an ellipse.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the thickness of the first covering layer is greater than that of the second covering layer;

The invention provides a storage chip and a preparation method of the storage chip, the storage chip provided by the invention comprises a storage wafer and a control wafer, and the storage wafer and the control wafer are stacked and are in bonding connection through a three-dimensional heterogeneous integrated structure; the storage wafer comprises a first substrate and a plurality of storage units, the control wafer comprises a second substrate and a plurality of control units, and the control units are connected with the storage units and control the storage units to perform read-write operation; the storage wafer comprises a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a two-dimensional material-based transistor. The memory chip has the characteristics of low power consumption and high data transmission speed, the preparation process of the control wafer is convenient to be compatible with the subsequent process of the chip, and the product reliability is high.

The present invention is entitled "Material Having Both Negative Spin Polarization and Negative Anisotropy." Aspects of the present disclosure generally relate to spintronic devices for use in magnetic media drives, magnetoresistive random access memory devices, magnetic sensors, or magnetic recording write heads. The spintronic device includes a multilayer structure having a negative anisotropy field and a negative spin polarization. The multilayer structure includes a plurality of layers, each of the plurality of layers including a first sublayer comprising Fe and a second sublayer comprising Co. At least one of the first sublayer and the second sublayer comprises one or more of Cr, V, and Ti. The first sublayers and the second sublayers alternate. The negative anisotropy field of the multilayer structure is between about -0.5 T and about -0.8 T, and the effective magnetization of the multilayer structure is between about 2.4 T and about 2.8 T.

The invention discloses a magnetoresistive random access memory element and a manufacturing method thereof. The magnetoresistive random access memory element comprises a bottom electrode, a spin-orbit torque layer, a magnetic tunnel junction and a top electrode. The spin-orbit torque layer is arranged on the bottom electrode, the magnetic tunnel junction is arranged on the spin-orbit torque layer, the top electrode is arranged on the magnetic tunnel junction, and the top electrode comprises a metal carbide layer.

A three-dimensional (3D) magnetoresistive random access memory (MRAM) device includes a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to a major surface of a substrate of the 3D MRAM device. Each cell of the first plurality of cells is separated by an insulating layer of the plurality of insulating layers from another cell of the plurality of cells. Each cell of the first plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type configured to interface with the MTJ structure of the cell. The first interconnect structure is oriented orthogonally to the second interconnect of each cell of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the top surface of the second covering layer is lower than the top surface of the first covering layer;

The present invention discloses a system architecture, structure and manufacturing method of a hybrid random access memory, wherein the hybrid random access memory for a single-chip system includes: a semiconductor substrate having a magnetoresistive random access memory region and a variable resistance random access memory region, a first dielectric layer located on the semiconductor substrate, a plurality of variable resistance random access memory cells located in the first dielectric layer of the variable resistance random access memory region, a second dielectric layer located on the first dielectric layer, and a plurality of magnetoresistive random access memory cells located in the second dielectric layer of the magnetoresistive random access memory region.

The invention provides a magnetoresistive random access memory circuit and a layout structure. Wherein each memory cell includes a first transistor having a first gate connected to a first word line, a first source, and a first drain, a second transistor having a second gate connected to a second word line, a second source, and a second drain, the first source electrode and the second drain electrode are respectively connected with the first source electrode and the first drain electrode, one end of the first magnetic tunneling junction is connected with the first drain electrode and the second drain electrode, and the other end of the first magnetic tunneling junction is connected with a first bit line; one end of the second magnetic tunnel junction is connected to the first drain electrode and the second drain electrode, the other end of the second magnetic tunnel junction is connected to a second bit line, and the source line is connected to the first source electrode and the second source electrode.

A magnetoresistive random access memory structure includes a substrate, a plurality of magnetoresistive random access memory cells on the substrate, wherein the magnetoresistive random access memory cells are located in a memory region, the memory region is adjacent to a logic region, and an ultra low dielectric constant layer covers the magnetoresistive random access memory cells, wherein a surface portion of the ultra low dielectric constant layer is doped with fluorine, and a surface of the ultra low dielectric constant layer at a boundary between the memory region and the logic region has a notch.

The invention provides a memory chip and a preparation method of the memory chip, the memory chip provided by the invention comprises a substrate, and a memory layer and a control layer which are arranged on the substrate, the memory layer and the control layer are arranged on different planes, and the projections of the memory layer and the control layer on the substrate are at least partially overlapped; the storage layer comprises a plurality of storage units, the control layer comprises a plurality of control units, and the control units are connected with the storage units and control the storage units to perform read-write operation; the storage layer comprises a magnetoresistive random access memory; the control layer comprises a transistor; and the substrate, the storage layer and the control layer form the same wafer. The memory chip has the characteristics of low power consumption, high speed and high reliability.

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

The embodiment of the invention relates to a switching unit. An electronic unit includes an integrated stacked structure including, in order: a first electrode; a bidirectional threshold switch layer under the first electrode; and a fixed resistor under the bidirectional threshold switch layer. A second electrode may be included between the fixed resistor and the bidirectional threshold switching layer. A memory layer, such as a phase change material layer, a resistive random access memory layer, or a magnetoresistive random access memory layer, may be included between the first electrode and the bidirectional threshold switching layer.

The invention discloses a magnetic resistance type random access memory layout structure, each memory cell comprises a first word line, a third word line and a second word line which are sequentially arranged on a substrate at intervals and extend towards a first direction to cross an active area, a first magnetic tunnel junction located in a semiconductor back section metal layer, and a second magnetic tunnel junction located in a semiconductor back section metal layer, a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a first bit line, and a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a second bit line, wherein the first bit line and the second bit line are located at different metal levels in the semiconductor back-end metal layer, and a source line is connected to the first active region and the fourth active region.

The invention discloses a magnetoresistive random access memory and a magnetoresistive random access memory system, which are applied to the field of information storage, and the memory comprises a plurality of magnetic tunnel junction bits, a write-in driver, a first wire connected with one end of each magnetic tunnel junction bit, and a second wire connected with the other end of each magnetic tunnel junction bit, a first conductive electrode of the write-in driver is connected with the first end of the first wire, a second conductive electrode of the write-in driver is connected with the second end of the second wire, and the deviation value of the wire length between a plurality of loops formed by the first conductive electrode and the second conductive electrode through each magnetic tunnel junction bit is smaller than a preset deviation value. According to the invention, the deviation value of the routing length between a plurality of loops formed by the first conductive electrode through each magnetic tunnel junction bit and the second conductive electrode is smaller than the preset deviation value, so that the problem of over-high near-end writing voltage is avoided, the service life of the device is prolonged, and the reading efficiency of the memory is improved at the same time.

An embodiment of the invention provides a magnetoresistive random access memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium oxide (MgO); and a free layer, wherein the free layer includes a first cobalt iron boron (CoFeB) layer on top of the tunnel barrier layer; the spacing layer is positioned on the top of the first CoFeB layer; the second CoFeB layer is positioned on the top of the spacing layer; and a cap layer of MgO on top of the second CoFeB layer. Further, the first CoFeB layer and the second CoFeB layer are substantially depleted of boron (B) to respectively include a first region adjacent to the tunnel barrier layer and the cap layer, respectively, and a second region adjacent to the spacer layer, where the first region of the first CoFeB layer and the second CoFeB layer includes crystalline ferrocobalt (CoFe), and the second region of the first CoFeB layer and the second CoFeB layer includes an amorphous CoFe alloy.

A magnetoresistive random access memory mainly includes a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor disposed on a substrate, a magnetic tunneling junction (MTJ) disposed between the first MOS transistor and the second MOS transistor, a first interlayer dielectric layer disposed on one side of the MTJ and on the first MOS transistor, and a second interlayer dielectric layer disposed on the other side of the MTJ and on the second MOS transistor.