78 results about "Magnetoresistive random-access memory" patented technology

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

The invention provides a magnetoresistive random access memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a magnetic tunnel junction film layer on the substrate; forming a first dielectric layer on the magnetic tunnel junction film layer; etching the two ends of the first dielectric layer in the first direction so as to enable the two opposite ends of the magnetic tunnel junction film layer in the first direction to extend out of the etched first dielectric layer; forming a metal layer on the magnetic tunnel junction film layer, wherein the metal layer wraps the etched first dielectric layer; and etching the metal layer to form top electrodes on two opposite sides of the first dielectric layer along the first direction. According to the invention, the yield of the MRAM can be improved.

The invention discloses a magnetoresistive random access memory, which mainly includes a first array region and a second array region disposed on a substrate, a first magnetic tunneling junction (MTJ) disposed on the first array region, a first upper electrode disposed on the first MTJ, a second MTJ disposed on the second array region, and a second upper electrode disposed on the second MTJ, wherein the first upper electrode and the second upper electrode comprise different nitrogen-to-carbon ratios.

This document discloses a three-dimensional (3D) magnetoresistive random access memory (MRAM) device comprising a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to the main surface of a substrate of the 3D MRAM device. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer among the plurality of insulating layers. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type, the second interconnect structure being configured to interface with the MTJ structure of the cell. The orientation of the first interconnect structure is orthogonal to the second interconnect structure of each of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, forming a first oxide layer on the first cap layer, and forming a second cap layer on sidewalls of the first oxide layer. Preferably, a top surface of the second cap layer is higher than a top surface of the MTJ.

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

The invention discloses a magnetoresistive random access memory element and a manufacturing method thereof. The magnetoresistive random access memory element comprises a bottom electrode, a spin-orbit torque layer, a magnetic tunnel junction and a top electrode. The spin-orbit torque layer is arranged on the bottom electrode, the magnetic tunnel junction is arranged on the spin-orbit torque layer, the top electrode is arranged on the magnetic tunnel junction, and the top electrode comprises a metal carbide layer.

A three-dimensional (3D) magnetoresistive random access memory (MRAM) device includes a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to a major surface of a substrate of the 3D MRAM device. Each cell of the first plurality of cells is separated by an insulating layer of the plurality of insulating layers from another cell of the plurality of cells. Each cell of the first plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type configured to interface with the MTJ structure of the cell. The first interconnect structure is oriented orthogonally to the second interconnect of each cell of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the top surface of the second covering layer is lower than the top surface of the first covering layer;

The invention provides a magnetoresistive random access memory circuit and a layout structure. Wherein each memory cell includes a first transistor having a first gate connected to a first word line, a first source, and a first drain, a second transistor having a second gate connected to a second word line, a second source, and a second drain, the first source electrode and the second drain electrode are respectively connected with the first source electrode and the first drain electrode, one end of the first magnetic tunneling junction is connected with the first drain electrode and the second drain electrode, and the other end of the first magnetic tunneling junction is connected with a first bit line; one end of the second magnetic tunnel junction is connected to the first drain electrode and the second drain electrode, the other end of the second magnetic tunnel junction is connected to a second bit line, and the source line is connected to the first source electrode and the second source electrode.

A magnetoresistive random access memory structure includes a substrate, a plurality of magnetoresistive random access memory cells on the substrate, wherein the magnetoresistive random access memory cells are located in a memory region, the memory region is adjacent to a logic region, and an ultra low dielectric constant layer covers the magnetoresistive random access memory cells, wherein a surface portion of the ultra low dielectric constant layer is doped with fluorine, and a surface of the ultra low dielectric constant layer at a boundary between the memory region and the logic region has a notch.

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

The embodiment of the invention relates to a switching unit. An electronic unit includes an integrated stacked structure including, in order: a first electrode; a bidirectional threshold switch layer under the first electrode; and a fixed resistor under the bidirectional threshold switch layer. A second electrode may be included between the fixed resistor and the bidirectional threshold switching layer. A memory layer, such as a phase change material layer, a resistive random access memory layer, or a magnetoresistive random access memory layer, may be included between the first electrode and the bidirectional threshold switching layer.

The invention discloses a magnetic resistance type random access memory layout structure, each memory cell comprises a first word line, a third word line and a second word line which are sequentially arranged on a substrate at intervals and extend towards a first direction to cross an active area, a first magnetic tunnel junction located in a semiconductor back section metal layer, and a second magnetic tunnel junction located in a semiconductor back section metal layer, a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a first bit line, and a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a second bit line, wherein the first bit line and the second bit line are located at different metal levels in the semiconductor back-end metal layer, and a source line is connected to the first active region and the fourth active region.

An embodiment of the invention provides a magnetoresistive random access memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium oxide (MgO); and a free layer, wherein the free layer includes a first cobalt iron boron (CoFeB) layer on top of the tunnel barrier layer; the spacing layer is positioned on the top of the first CoFeB layer; the second CoFeB layer is positioned on the top of the spacing layer; and a cap layer of MgO on top of the second CoFeB layer. Further, the first CoFeB layer and the second CoFeB layer are substantially depleted of boron (B) to respectively include a first region adjacent to the tunnel barrier layer and the cap layer, respectively, and a second region adjacent to the spacer layer, where the first region of the first CoFeB layer and the second CoFeB layer includes crystalline ferrocobalt (CoFe), and the second region of the first CoFeB layer and the second CoFeB layer includes an amorphous CoFe alloy.

A magnetoresistive random access memory mainly includes a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor disposed on a substrate, a magnetic tunneling junction (MTJ) disposed between the first MOS transistor and the second MOS transistor, a first interlayer dielectric layer disposed on one side of the MTJ and on the first MOS transistor, and a second interlayer dielectric layer disposed on the other side of the MTJ and on the second MOS transistor.

Embodiments of the present disclosure relate to switching cells. An electronic cell includes an integrated stack structure including, in order: a first electrode; a bidirectional threshold switching layer below the first electrode; and a fixed resistor below the bidirectional threshold switching layer. A second electrode can be included between the fixed resistor and the bidirectional threshold switching layer. A memory layer, such as a phase change material layer, a resistive random access memory layer, or a magnetoresistive random access memory layer, can be included between the first electrode and the bidirectional threshold switching layer.

A spin-orbit torque (SOT) magnetic device with synthetic antiferromagnetic (SAF) structure, including a SOT layer for providing a spin current, a SAF structure composed of a first ferromagnetic layer, a nickel oxide (NiO) exchange coupling layer and a second ferromagnetic layer, and a capping layer on the SAF structure. This magnetoelectric device of oxide SAF structure can achieve zero-field switching through current-induced SOT, and can be used as the free layer of a magnetoresistive random access memory (MRAM).

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the method for manufacturing a magnetoresistive random access memory (MRAM) element mainly comprises the steps: providing a substrate comprising an MRAM region and a logic region, forming a first intermetallic dielectric layer on the substrate, forming a metal nitride layer on the first intermetallic dielectric layer, forming a second intermetallic dielectric layer on the first intermetallic dielectric layer, forming a second metal nitride layer on the second intermetallic dielectric layer, and forming a second metal nitride layer on the second intermetallic dielectric layer. Removing the metal nitride layer in the logic region by using a first patterning mask, removing the metal nitride layer in the MRAM region by using a second patterning mask, and removing the first intermetallic dielectric layer in the MRAM region and the logic region by using a third patterning mask, the method comprises the steps of forming a first metal interconnector in an MRAM region and forming a second metal interconnector in a logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnector.

A magnetoresistive random access memory ("MRAM" for short) device includes at least one MRAM array. Each MRAM array includes a reference cell and a reference generator that generates a reference voltage between a first voltage and a second voltage, the first voltage being a function of a first current flowing through the first reference cell and the second voltage being a function of a second current flowing through the second reference cell, the first reference cell and the second reference cell are a pair of reference cells storing complementary values in a row of the MRAM array. Reference voltage can be automatically centered and track reading current changes of all PVT angles, and the reference voltage does not need to be adjusted. In some embodiments, the reference generator is used in cooperation with a current detection amplifier, and correct read data of all PVT angles can be reliably output.

A magnetoresistive random access memory (MRAM) structure is provided that includes a chiral spin-orbit-torque (SOT) metal bottom electrode under the bottom magnetic free layer where the chiral SOT metal bottom electrode is surrounded by a via dielectric. The chiral SOT metal bottom electrode enables the charge current, spin current and spin polarization directions to be in the same direction which is perpendicular to the surface of the chiral SOT via structure.

A layout pattern of a magnetoresistive random access memory is disclosed. The layout pattern includes first and second diffusion regions extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, first and second gate patterns extending along the second direction on one side of the first contact plug, and third and fourth gate patterns extending along the second direction on the other side of the first contact plug.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a dielectric layer on the MTJ, performing a first etching process to form a first trench in the dielectric layer, and performing a second etching process to form a second trench in the dielectric layer. Preferably, a bottom surface of the second trench is lower than a bottom surface of the first trench, a width of the second trench is less than a width of the first trench, and the first trench and the second trench together form a step profile.

A semiconductor device includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer, and a reference layer on a second side of the tunnel barrier layer opposite the first side.

A memory device such as a magnetoresistive random access memory is provided that includes a magnetic tunnel junction containing structure having a lower portion including a first magnetic material layer, and an upper portion including a second magnetic material layer in which the upper portion of the MTJ containing structure is off-set relative to the lower portion.

Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.

An embedded magnetoresistive random access memory (MRAM) device is provided in which a top metal contact composed of a subtractable etchable metal is in contact with a magnetic tunnel structure (MTJ) structure. An air gap is present surrounding the MTJ structure to reduce capacitance and enable the reduction of the RC (resistance-capacitance) time constant of the MRAM device at tight pitches.

A magnetoresistive random access memory includes: a lower metal layer and a lower dielectric layer, disposed on a semiconductor substrate, and the lower metal layer disposed in the lower dielectric layer; a dielectric layer, disposed on the lower dielectric layer and the lower metal layer; a via plug, a magnetic tunnel junction and an additional metal layer, disposed in the dielectric layer, wherein the via plug is electrically connected to the lower metal layer, the magnetic tunnel junction is disposed on the via plug and the additional metal layer is disposed on the magnetic tunnel junction; an upper dielectric layer, disposed on the dielectric layer and the additional metal layer; and an upper via plug and an upper metal layer, disposed in the upper dielectric layer, wherein the upper via plug is electrically connected to the additional metal layer.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.