40results about How to "Eliminate Offset Voltage" patented technology

A Hall sensor has a P-type semiconductor substrate and a Hall sensing portion having a square shape and an N-type conductivity disposed on a surface of the semiconductor substrate. The Hall sensor includes Hall voltage output terminals having the same shape with each other, and control current input terminals having the same shape with each other. The Hall voltage output terminals are disposed at respective ones of four vertices of the Hall sensing portion. The control current input terminals include pairs of control current input terminals disposed at respective ones of the four vertices of the Hall sensing portion and arranged on both sides of respective ones of the Hall voltage output terminals in spaced apart relation from the Hall voltage output terminals so as to prevent electrical connection between the control current input terminals and the Hall voltage output terminals.

The present invention relates to a comparison device and a digital analog converter used the same, which includes a first and second comparators, a chop switching unit, a delta-sigma modulation unit, and a first and second compensation units. The chop switching unit transmits a first and a second signals to two input terminals of the first comparator during a first period, and inverses the first and second signals during a second period. The delta-sigma modulation unit compares the comparison results of two parallel comparators and generates the digital control codes for the comparators with the awareness of the chop switching unit. The first and the second compensation units adjust the threshold voltages of the comparators according to the digital control codes and a step size for calibrating the offset voltages of two comparators.

In a Hall sensor in which a Hall element and elements serving as heat sources out of components of a circuit for driving the Hall element are arranged close to each other on a silicon substrate, two directions of control currents by spinning current for the Hall element are selected in a vector manner based on signals from temperature sensors arranged close to a periphery of the Hall element, thereby enabling the elimination of a magnetic offset caused by heat generation of the heat sources.

Provided is a highly-sensitive Hall element capable of eliminating an offset voltage without increasing the chip size. The Hall element includes: a Hall sensing portion having a shape of a cross and four convex portions; Hall voltage output terminals which are arranged at the centers of the front edges of the four convex portions, respectively; and control current input terminals which are arranged on side surfaces of each of the convex portions independently of the Hall voltage output terminals. In this case, the Hall voltage output terminal has a small width and the control current input terminal has a large width.

Provided is a Hall sensor having an element that, among Hall elements and circuitry for driving semiconductor Hall elements, serves as a heat source, wherein it is possible to eliminate offset voltage with no increase in the chip size. This Hall sensor is characterized in that, in two pairs of elements, a Hall element control current (1) flowing between one of the pairs of elements and a Hall element control current (2) flowing between the other pair of elements interact as vectors, the Hall elements have a linear-symmetric shape in relation to a straight line taken along the vector sum of the Hall element control current (1) and the Hall element control current (2), and the element that serves as the heat source is positioned such that the center of the heat source lies on the straight line taken along the vector sum of the Hall element control current (1) and the Hall element control current (2).

The invention provides an offset calibration method and an offset calibration circuit with the radio frequency data path. The method comprises: two input terminals of an equalizer are switched to a common voltage at a first time point, wherein the equalizer generates a first equalized signal and a second equalized signal according to the common voltage. It is determined whether a first offset voltage is present in the equalizer according to the first and second equalized signals generated from the common voltage. If the first offset voltage is determined to be present in the equalizer, a first compensation voltage is provided to the equalizer. The offset calibration method and the offset calibration circuit with the radio frequency data path of the invention can eliminate the offset voltage of the radio frequency data path and enhance the data reading quality via processing the offset calibration for two phases of the radio frequency data path.

The present invention provides a low offset comparator and offset cancellation method thereof. The low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage.

The vertical Hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer.

The invention relates to a diode infrared detector readout integrated circuit with a self-stabilization zero circuit. The diode infrared detector readout integrated circuit comprises a transistor, wherein the drain end of the transistor is connected with the self-stabilization zero circuit; the self-stabilization zero circuit comprises a main operational amplifier and a secondary operational amplifier; the same-phase end of the main operational amplifier is connected with the phi 1 end of a first single-pole double-throw switch and the same-phase end of the secondary operational amplifier; the output end of the secondary operational amplifier is connected with the single end of a second single-pole double-throw switch; the phi 1 end of the second single-pole double-throw switch is connected with the first end of a secondary operational amplification capacitor and the auxiliary input end of a secondary operational amplifier; the second end of the secondary operational amplification capacitor is connected with the second end of a main operational amplification capacitor; and the first end of the main operational amplification capacitor is connected with the phi 2 end of the second single-pole double-throw switch and the auxiliary input end of a main operational amplifier. By the diode infrared detector readout integrated circuit, the problem of large breakover voltage drop in a diode infrared detector can be solved effectively, offset voltage and low-frequency noise are eliminated, and the integration level and signal to noise ratio of a system are improved; and the diode infrared detector readout integrated circuit is large in dynamic range, safe and reliable.