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Low offset comparator and offset cancellation method thereof

A technology of offset elimination and comparator, applied in multiple input and output pulse circuits, etc.

Inactive Publication Date: 2011-04-06
HIMAX TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The input voltage Vin received by the comparator 200 is fed in in the form of DC coupling, so the input range of the comparator 200 is relatively small
In addition, the gain value A of the pre-amplifier 210 should not be too large. If the gain value A is too large, the offset voltage will be amplified and the pre-amplifier 210 will hang up.

Method used

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  • Low offset comparator and offset cancellation method thereof
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  • Low offset comparator and offset cancellation method thereof

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Embodiment Construction

[0031] Then, in a tracking mode, the series input offset storage stages 321-32N, the second output offset storage stage 330 and the first output offset storage stage 310 are sequentially separated from the offset elimination mode, and then the preamplifier 305 amplifies the input voltage Vin. The input offset and the output offset stored in the offset cancellation mode are respectively canceled with a plurality of offset voltages generated by the low offset comparator 300 . Afterwards, in a latch mode, the latch 340 is triggered (strobe) by the amplified input signal output by the pre-amplifier 305, and accordingly outputs a logic level Vout, which is an identifiable voltage level.

[0032] The first output offset storage stage 310 includes a first rail-to-rail amplifier 3101, 2 first output offset storage Co1, 2 first output offset storage switches Soos1, and 2 first switches S1. The first rail-to-rail amplifier 3101 has 2 input terminals and 2 output terminals. The first...

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PUM

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Abstract

The present invention provides a low offset comparator and offset cancellation method thereof. The low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage areconfigured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage.

Description

technical field [0001] The present invention relates to a low offset comparator and its offset elimination method, and in particular to a low offset comparator and its offset elimination method which more effectively eliminates the offset voltage and has high circuit operation speed. Background technique [0002] In the comparator, a small amount of noise may affect the circuit operation results, and due to the mismatch of the components, the comparator will generate an offset voltage when performing the amplification operation, so the technology of offset cancellation (offset cancellation) must be used to perform compensation operations. There are two commonly used technologies for offset elimination, namely input offset storage (input offset storage, IOS) and output offset storage (output offset storage, OSS). [0003] Please refer to figure 1 , which shows the circuit diagram of a conventional comparator using input offset memory technology. The comparator 100 includes...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/24
CPCH03K5/24
Inventor 黄志豪
Owner HIMAX TECH LTD
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