The present disclosure provides a
memory cell, comprising: a stack layer laminated on a substrate, comprising: a plurality of channel holes penetrating through the stack layer and part of the substrate; wherein at least one second laminated material layer in the stack layer after forming the plurality of channel holes is etched to form a ring-shaped limiting structure; a
gate dielectric layer located on the surface of the plurality of channel holes after the ring-shaped limiting structure is etched; a channel layer located on the surface of the
gate dielectric layer; a resistance variable layer located on the surface of the channel layer corresponding to the ring-shaped limiting structure; wherein the
gate voltage applied to the at least one second laminated material layer and the
bit line pulse
signal connected with the channel layer are controlled to change the resistance state of the resistance variable layer, so as to realize the reading, writing or erasing operation of the
memory cell on the resistance variable layer. The present disclosure also provides a preparation method of the
memory cell, a three-dimensional memory and an operation method thereof.