302results about "DC level change" patented technology

Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

A baseline wander correcting unit is provided in a processing path in which a predetermined processing is performed on an input signal. The baseline wander correcting unit includes a baseline wander derivation unit which derives an amount of wander of baseline of a signal on which the predetermined processing has been performed, and an adjustment unit which adjusts an amount of wander of the baseline derived by the baseline wander derivation unit and outputs a baseline correction amount, so that the baseline wander correcting unit corrects the baseline wander by a feedforward control. The correction by the feedforward control ensures the baseline wander in the event of an instantaneous wander.

In one embodiment of the present invention, a method for adjusting a signal includes applying at least one of a loss compensation for frequency-dependent distortion and an offset compensation for DC-offset distortion to a signal before or after the distortion occurs to generate an output signal, the output signal comprising even phase and odd phase. The method also includes selecting either the even phase or the odd phase at which to begin sampling. The method further includes, using a clock signal, beginning at the selected phase, sampling the output signal to generate a plurality of data values and an error value, the error value indicating residue of the distortion based on the sampling of the output signal. The method also includes adjusting none, one, or more of the loss compensation and the offset compensation applied to the signal based on the sampled error value. The method further includes, after adjusting the at least one of the loss compensation and the offset compensation applied to the signal based on the sampled error value, selecting either the even phase or the odd phase at which to begin the next sampling.

A display device has a driver including a level converter formed of polysilicon MISTFTs. The level converter includes first, second and third N-channel MISTFTs (NMISTFTs) and first, second and third P-channel MISTFTs (PMISTFTs). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.

A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount. The fine correcting by the first baseline wander correcting unit and the coarse correcting by the second baseline correcting unit ensure efficient correction of baseline wander.

An output power limiter system (PLS) for audio amplifiers may be designed as a feedback control system for protection of the load and/or quality of the audio experience. The PLS may use comparator to sense the output current, compare it to a specified threshold, and assert a signal when the output current reaches and exceeds the specified threshold. The output signal from the comparator may enable a counter that is clocked with a high frequency clock to begin counting to measure the pulse-width of the comparator output. The output of the counter may be averaged through a fast attack and slow release infinite impulse response (IIR) filter having programmable settings to generate a rate of attenuation or rate of release that adjusts a gain correction in terms of decibels (dB). The output of the IIR filter may then be used for attenuating the output current.

One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system transmits a signal through a capacitive transmitter pad and receives a corresponding input signal through a capacitive receiver pad. The system amplifies the input signal by feeding it through a number of cascaded CMOS inverters operating from ever-increasing power supply voltages from the first to the last inverter. The system periodically initializes the input voltage of the first CMOS inverter by: suspending data transmission on the capacitive transmitter pad and setting the voltage on the capacitive transmitter pad to a middle point between a voltage that represents logic “1” and a voltage that represents logic “0”, coupling the output of the first CMOS inverter to its input through a switch, and, after the input voltage of the first CMOS inverter stage substantially stabilizes at the switching threshold, uncoupling the output of the first CMOS inverter stage from the input of the first CMOS inverter stage and then resuming data transmission on the capacitive transmitter pad.

An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique.

A first peak hold circuit holds a peak potential of a positive phase voltage signal output from a differential output amplifier, and a second peak hold circuit holds a peak potential of a negative phase voltage signal output from the differential output amplifier. An adding circuit adds an output signal of the first peak hold circuit and an output signal of the second peak hold circuit. A differential input amplifier amplifies and outputs a voltage difference between a reference voltage and an addition result voltage signal of the adding circuit. A current output circuit outputs a DC current based on an output voltage of the differential input amplifier. A current switch circuit converts a DC current to a pulse current so as to supply the pulse current to a laser diode.

Methods and apparatus are provided for separating DC and AC components of a composite signal Is=Idc+Iac from a current source, e.g., a photodiode current source. Four current mirrors CM-1 . . . CM-4 are used with common branches and overlap. CM-1 through CM-3 mirror Is and CM-4 mirrors Idc where lac has been removed by a frequency selective branch. Outputs of the Cm-3 and Cm-4 are combined at a node to provide a signal proportional substantially only to Iac. Complementary devices are used where Cm-1 and Cm-4 are of one type and Cm-2 and Cm-3 are of opposite type. The arrangement allows detection of AC signals (e.g., pulses) that are orders of magnitude smaller than the DC background. An I-to-V converter with a large feedback resistance is used at the output to produce a comparatively large voltage output proportional to lac.

When a voltage is applied from outside such that a current flowing in a Hall element is switched, each of a plurality of capacitors is charged with an output voltage of the Hall element in each state. A dummy switching element is connected to a switching element which connects the plurality of capacitors in parallel to each other, the dummy switching element and the switching element being controlled to be switched ON and OFF exclusively with respect to each other.

The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

In a semiconductor device, at least one operational amplifier drives a capacitive load in accordance with a control signal. A bias changing circuit receives the control signal to generate a bias changing signal in synchronization with the control signal dependent upon a width of the control signal. A bias circuit controls a bias current flowing through the operational amplifier in accordance with the bias changing signal.

Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Disclosed herein is an apparatus for receiving a wide-band pulse signal in a communication channel using a human body. When a weak wide-band pulse signal, which is output from a communication channel using a human body as a data transmission medium, is restored to a digital signal, it is possible to accomplish low power consumption and high data transmission rate using a wide-band symmetrical triggering technology using 50-Ω impedance matching, wide-band amplification and symmetrical threshold voltages. In addition, since only a single signal electrode is used, it is possible to provide an apparatus having usability, wearability and miniaturization. In addition, it is possible to remove necessities of an external reference voltage to reduce area consumption and to simply adjust a feedback resistor to easily adjust the reception sensitivity according to a communication distance.