Super structure based on vertical gate SOI CMOS device and manufacturing method thereof

Abstract

The invention discloses a super structure based on a vertical gate SOI CMOS device and a manufacturing method thereof. The structure comprises an SOI substrate, a gate region, a source region, a channel region, a drift region and a drain region, wherein the gate region, the source region, the channel region, the drift region and the drain region grow on the SOI substrate; the gate region is vertical to and in direct contact with a buried oxide layer; the drift region in which pn column regions are arranged up and down is arranged between the channel region and the drain region; and the doping type of the lower column region in the drift region is consistent with the doping type of the drain region. On the basis of the vertical gate SOI CMOS device, the invention transforms the single doping type drift region into the drift region in which the pn column regions are arranged alternately, enables the drift region to be fully exhausted as much as possible when the breakdown voltage is achieved, optimizes the distribution of each electric field, reduces and levels the peak values of electric fields at the drift region, the junction of the drift region and the channel region and the junction of the drift region and the drain region, keeps the function of the vertical gate SOI CMOS device for eliminating the floating-body effect, and simultaneously greatly improves the high-voltage breakdown resistance of the SOI LDMOS.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and solid electronics, and relates to a superjunction structure based on a vertical gate SOI CMOS device and a manufacturing method thereof. Background technique [0002] SOI (Silicon-On-Insulator) integration technology is known as the integration technology of the 21st century due to its advantages of good isolation performance, small leakage current, fast speed, low power consumption and radiation resistance, and is widely used in high-end Performance HVIC and PIC. [0003] However, due to the dielectric isolation of SOI materials, Si-SiO 2 The depletion layer at the interface is not in contact, and there is a neutral body region between them. This neutral body region makes the silicon body in an electrically floating state, resulting in two obvious secondary parasitic effects, one is "warping Effect", that is, the Kink effect; the other is the base open-circuit NPN parasitic transis...

AI Technical Summary

Problems solved by technology

The unique floating body effect of SOI CMOS devices will not only reduce device gain, reduce source-drain breakdown voltage, cause single-transistor latch-up, bring large leakage current, increase power consumption, but also cause circuit instability, resulting in Noise overshoot that can have a significant impact on device and circuit performance

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