CMOS VLSI Integrated Fabrication Method of Vertical Trench soi LDMOS

Abstract

The invention relates to a CMOS VLSI integrated manufacturing method of vertical channel SOI LDMOS. The SOI LDMOS device manufactured by the existing method has no vertical channel structure and corresponding excellent performance. The present invention realizes vertical grid and grid field plate structure, stepped trench drain structure by adopting trench etching technology, well doping is adjusted to reverse doping distribution ion implantation well and well ohmic contact doping process, in the source region It is realized by doping the gate and drain at the same time. The invention adopts the existing SOI CMOS VLSI process technology, under the condition of slightly increasing process complexity and process cost, the electrical and thermal properties of integrated power and radio frequency SOILDMOS devices are significantly improved.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to SOI (semiconductor on insulating layer) CMOS (complementary metal-oxide - Semiconductor) VLSI (Very Large Scale Integration) integrated manufacturing method. Background technique [0002] Due to its small size, weight, high operating frequency, high operating temperature, strong radiation resistance, low cost and high reliability, SOI LDMOS devices are used as non-contact power electronic switches , power drivers, or RF power amplifier transistors are widely used in technical fields such as intelligent power electronics, high-temperature environment power electronics, space power electronics, vehicle power electronics, and communications. SOI CMOS VLSI process technology has advantages such as high process maturity, good dielectric isolation performance, simple isolation process, easy three-dimensional integration, easy integration of micro-optical electromechanical and p...

AI Technical Summary

Problems solved by technology

[0012] When the SOI LDMOS device is turned on, its conductive channel is located on the front surface of the top layer and is a lateral channel. The gate field plate covers the thicker field oxide layer, resulting in the concentration of the on-state current to the front surface of the drift region and large expansion resistance. , the conductance modulation effect in the drift region is uneven, the on-state resistance is large, the on-state voltage drop is high, the on-state current is small, and the on-state power consumption is high, the working efficiency of the device is low, and the temperature rises quickly, which is not conducive to improving the reliability of the device and system. Save energy and protect the environment