46results about How to "Realize the process is simple" patented technology

The invention discloses a GaAs PIN diode, which comprises: a semi-insulating GaAs underlay for supporting the whole GaAs diode; a high doped layer N growing in extension on the semi-insulating GaAs underlay, resistive formations I and P close to eigen growing in extension in turn on the high doped layer N; By wet process and etching, the areas of the said high doped layer N, resistive formations I and P reduced in turn to form a mesa structure; a top electrode of the round structure formed by metal evaporator on layer P; a semi-orbicular bottom electrode formed by metal evaporator on layer N. The invention also discloses a manufacturing method of GaAs PIN diode. The invention efficiently lowers the parasitic capacitance of the PIN diode without increasing the difficulty of the process and simultaneously greatly shortens the microstrip line connected with the top electrode. The spurious inductance brought by the invention can be greatly reduced or even omitted without using the air-bridge process. The invention has the advantages of easy making, better high frequency characteristic, which is easy to realize the single scale integration.

The invention relates to a semiconductor glue used in electrical products, which contains 55-65% of glue, 79-81% of epoxy glue, 7-9% of curing agent, and 11-13% of toughening agent by weight percentage. %; filler 31-41%, including graphite 58-62%, kaolin 38-42%; low temperature curing agent 2-4%. Heat the epoxy glue into a fluid in an oven at 50-60°C; take the liquid epoxy glue in a beaker, and place it in a constant temperature water bath at 50-60°C; while stirring, add curing agent, toughening agent and thinner in sequence until stirring Evenly; add the filling and stir well. The invention solves the technical problem of poor reliability and safety of shielding in the background technology. The invention has simple process and high production efficiency, and can be used for electrostatic shielding or forming semiconductor layers.

The invention relates to the technical field of display, and provides a manufacturing method of an array substrate. The method comprises the following steps: forming an initial gate, wherein, the edgeof the initial gate has a slope; A preset thick bottom etching is performed on a slope surface of the initial gate edge and a partial plane extending inwardly of the slope surface, thereby reducing aslope angle of the initial gate slope surface. The present disclosure reduces the slope angle of the initial gate edge slope surface by performing a preset thick bottom etching on the slope surface of the initial gate edge and a portion of the plane in which the slope surface extends inwardly, thereby reducing the probability of a fracture or void occurring between the initial gate and the interlayer insulating layer.

The invention discloses a multifunctional socket, which comprises a base and a panel, wherein the panel is provided with three jacks which are matched with a three-jack plug, the area between the upper side of the left inclined jack and the ground line jack is provided with a fourth jack which is parallel with the right inclined jack, the fourth jack is matched with the right inclined jack, and a fourth inserting sheet is electrically connected with a left inclined inserting sheet. The multifunctional socket has the advantages that the function of a two-jack socket and the function of a three-jack socket are realized by the four-jack socket; the fourth jack in the inserting plate is arranged close to or is in linear contact with the left inclined jack or the right inclined jack, so the structure is compact, the surface area of the panel is minimum, the material is furthest saved, and the safety is high; and the structure design is reasonable, the production and the manufacture are easy, and the popularization and the application are favorable.