Manufacturing method of array substrate, array substrate and display device

Abstract

The invention relates to the technical field of display, and provides a manufacturing method of an array substrate. The method comprises the following steps: forming an initial gate, wherein, the edgeof the initial gate has a slope; A preset thick bottom etching is performed on a slope surface of the initial gate edge and a partial plane extending inwardly of the slope surface, thereby reducing aslope angle of the initial gate slope surface. The present disclosure reduces the slope angle of the initial gate edge slope surface by performing a preset thick bottom etching on the slope surface of the initial gate edge and a portion of the plane in which the slope surface extends inwardly, thereby reducing the probability of a fracture or void occurring between the initial gate and the interlayer insulating layer.

Description

technical field [0001] The present disclosure relates to the technical field of displays, and in particular, to a manufacturing method of an array substrate, the array substrate and a display device. Background technique [0002] Recently, large-size OLEDs have gradually become a new growth hotspot for TVs due to their high contrast and self-illumination. Among them, the top gate of large-size OLEDs has a higher on-state current (Ion), higher aperture ratio and better stability than the bottom gate. Having attention. [0003] In the top-gate design, the gate, drain, and source are located on the same side of the channel layer, and the gate, drain, and source are separated by an interlayer insulating layer. [0004] However, in the related art, the gate is usually formed by a wet etching process. During the wet etching process, the upper part of the gate is etched in the wet etching solution for a long time. Therefore, the edge of the gate formed by the wet etching process ...

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Problems solved by technology

[0004] However, in the related art, the gate is usually formed by a wet etching process. During the wet etching process, the upper part of the gate is etched in the wet etching solution for a long time. Therefore, the edge of the gate formed by the wet etching process with slope structure

When the slope angle of the slope is large, cracks or gaps are likely to appear between the gate and the interlayer insulating layer, resulting in the connection between the gate and the source or drain, affecting the normal display

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