300results about How to "Reduce parasitic inductance" patented technology

The invention discloses a substrate embedded power device packaging structure comprising: a substrate having a metalized through hole and a first power chip embedding slot; a first power chip disposedin the first power chip embedding slot; a photo-imageable dielectric (PID) covering the upper and lower sides of the substrate, and provided with an upper opening and a lower opening at positions corresponding to the metalized through hole and the electrode of the first power chip; an upper metal layer disposed on the upper surface of the PID and in the upper opening, and in electric interconnection to the first surface electrode of the first power chip and the metalized through hole; a lower metal layer disposed on the lower surface of the PID and in the lower opening, and in electric interconnection to the second surface electrode of the first power chip and the metalized through hole; an upper solder resist layer covering the upper metal layer; a lower solder resist layer covering thelower metal layer; and a metalized bonding pad.

The invention discloses a double-surface low-parasitic inductance GaN power integrated module. The double-surface low-parasitic inductance GaN power integrated module comprises an upper bridge arm apparatus, a lower bridge arm apparatus and a bus capacitor. The upper bridge arm apparatus and the lower bridge arm apparatus are LGA packaged GaN apparatuses, and the bus capacitor uses chip packaging. One apparatus is arranged at the front surface of a substrate while the other is arranged at the reverse surface of the substrate, and the source electrode of the upper bridge arm apparatus is opposite to the drain electrode of the lower bridge arm apparatus and directly connected with the drain electrode of the lower bridge arm apparatus through holes. The bus capacitor is arranged at two sides of the upper bridge arm apparatus. The arrangement mode of the double-surface low-parasitic inductance GaN power integrated module is capable of effectively reducing the area of a high-frequency power loop and completely uses the crossed structure of LGA packaging drain electrodes and source electrodes to form a plurality of crossed and parallel high-frequency power current loops, and accordingly the parasitic inductance of the high-frequency power loops is greatly lowered, and the over-voltage and oscillation are effectively reduced in the switching process.

In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.

The invention discloses a flexible-substrate-based passive wireless pressure sensor with a self-packaging function. The pressure sensor comprises an upper flexible substrate, an upper metal layer, a middle flexible substrate, a lower metal layer and a lower flexible substrate, which are sequentially arranged from top to bottom and fixedly connected. An electric through hole and a cavity are formed in the middle flexible substrate. The upper metal layer comprises a planar inductance coil and a capacitor upper polar plate positioned on the middle part of the planar inductance coil. An inner connector of the planar inductance coil is connected with the capacitor upper polar plate. The lower metal layer comprises a capacitor lower polar plate opposite to the upper plate capacitor and an interconnecting wire connected with the capacitor upper polar plate. The sizes of the capacitor upper polar plate and capacitor lower polar plate are the same. An outer connector of the planar inductance coil of the upper metal layer is connected with the interconnecting wire of the lower metal layer through a conductive medium column in the electric through hole. The cavity of the middle flexible substrate is positioned between the capacitor upper polar plate and capacitor lower polar plate. The pressure sensor has the high performance of self packaging, non-contact, high sensitivity and high quality factor.

The invention discloses a double-sided cooling power module based on multi-area parallel arrangement. A metal insulating substrate connected with a negative power terminal is provided with annular insulating slots, and metal layers surrounded in the annular insulating slots are connected with upper half bridge chips through metal blocks and are connected with lower half bridge chips through metal blocks; or, a metal insulating substrate connected with a positive power terminal is provided with annular insulating slots, and lower half bridge chips and upper half bridge chips are sintered on metal layers surrounded in the annular insulating slots. Two metal insulating substrates are laminated, annular insulating slots are arranged in one metal insulating substrate, and metal layers and metal blocks are sintered inside the power module, and therefore, the area of a commutation circuit is reduced and the parasitic inductance of the module is greatly reduced. Moreover, the positive and negative power terminals laminated can be easily connected with an external bus, the area of the metal layers is increased as much as possible, the lead resistance of the module is reduced, and the parasitic inductance is significantly reduced.

The invention discloses a packaging structure of a power module. The packaging structure comprises a lower layer metal direct bonded ceramic circuit board, a packaged power device chip, an upper layer metal direct bonded ceramic circuit board, an upper cover plate and an insulating shell, wherein an electrode on the lower surface of the packaged power device chip is fixed on the lower layer ceramic circuit board through solder; the upper layer ceramic circuit board is inversely arranged on the packaged power device chip, and is in contact with an electrode on the upper surface of the packaged power device chip through a convex contact on the metal layer thereof; and the upper cover plate applies downward pressure to the upper layer ceramic circuit board through a compression spring to ensure tight contact between the convex contact and the electrode. By virtue of the packaging structure of the power module disclosed by the invention, lead bonding in the conventional power module packaging can be avoided, so that current carrying capacity is improved; and in addition, the packaging structure is simple and compact in structure, easy to realize, high in power device compatibility, and capable of improving heat dissipation of the power module and enhancing reliability of the power module.

The invention provides a 3D integrated framework of an ultrahigh frequency power converter. The 3D integrated framework comprises a PCB circuit layer and a winding unit erected on the PCB circuit layer. The winding unit is connected with the PCB circuit layer through a wire. The winding unit comprises winding layers formed on a first insulating layer and a first soft magnetic thin film layer formed on a second insulating layer. The first soft magnetic thin film layer is arranged below the winding layers in a laminated mode to be used for achieving magnetic shielding between the winding layers and the PCB circuit layer. Compared with the prior art, by the adoption of 3D integration, the size of the converter is reduced, and the power density is increased; soft magnetic materials are adopted to form the magnetic shielding layer, magnetic field interference between windings and the PCB circuit layer and between the windings and external metal is solved, the Q value of the windings is increased, the alternating current resistance and high-frequency loss of an inductor and a transformer are reduced, and the working efficiency of the converter is improved; a plane magnetic element is further adopted, and the miniaturization and flattening of products are guaranteed; temperature rising of the magnetic element is reduced greatly, and the working environment of a semiconductor device is improved.

The invention discloses a packaging structure and a packaging method for a silicon carbide power device. The packaging structure comprises a direct bond copper (DBC) ceramic substrate, a silicon carbide power device, a PCB, leads and a shell and forms a half-bridge circuit structure formed by the silicon carbide power device. According to the packaging structure and the packaging method provided by the invention, the area of a power circuit can be effectively reduced, conductors with opposite current flowing directions are formed during a commutation process by a switch transistor, mutual inductance offset is used for reducing parasitic inductance of a commutation circuit, and overvoltage and oscillation during the switching process can be effectively reduced; driving signal leads adopt a Kelvin connection mode and are vertical to power leads, a role of effectively reducing coupling between a driving circuit and a power circuit is played, and driving stability is enhanced; the DBC substrate and the PCB are welded thoroughly, and packaging reliability is enhanced; and power terminals and signal terminals are directly included in the PCB, thereby reducing contact resistance and parasitic inductance brought by extra terminals and achieving effects of reducing the cost.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. Silicon carbide deep P injection is performed in a specified region, groove etching and deposition of metal or polysilicon are performed above a silicon carbide deep P doped region, and the deposited metal or polysilicon is in direct contact with the silicon carbide N-epitaxy to form a Schottky contact or aSi/SiC heterojunction contact having rectifying characteristics. Therefore, the integration of multiple sub-rectifiers is achieve while optimizing the basic performance of the conventional silicon carbide UMOSFET, the working performance of the third quadrant of the device is greatly optimized, the gate-drain capacitance of the device is reduced and the switching speed of the device is improved.

The invention relates to a modular socket used for high-speed communication; in particular, a compensation capacitor is arranged on a transmission line to eliminate the interference generated by the parasitic capacitance between adjacent bolts, meanwhile a high-speed communication interference compensation pattern for a second compensation capacitor and a modular socket containing the pattern arealso arranged on the transmission line. The high-speed communication interference compensation pattern and the modular socket containing the pattern include the following units: a casing formed by a bolt buckle positioned at the lower end of a plug faucet and used for fixing the bolt and a combination guiding plate; a multilayer structure type printed circuit board with a plurality of bolts and IDC terminals communicated and combined at the upper part and with a plurality of compensation capacitors; a lower connecting block with the bottom surface combined with the printed circuit board and insliding combination along the combination guiding plate of the casing; and an upper connecting block combined with the upper part of the lower connecting block, cutting a UTP cable leaded from the rear part and connecting the pieces of the UTP cable to the IDC terminals.

The invention discloses a metal-oxide-metal capacitor structure. The capacitor structure is characterized in that on the same-layer metal, a first electrode of a capacitor consists of a first group of metal strips which are mutually parallel, and the first group of metal strips which are mutually parallel are connected with a metal strip vertical to the first group of metal strips which are mutually parallel; or the first electrode of the capacitor consists of a stack-shaped metal strip; on the same-layer metal, a second electrode of the capacitor consists of a second group of metal strips which form an interpolation structure with the first electrode of the capacitor; and the same-layer metal structure is a minimum repeating unit so as to form an MOM (Metal-Oxide-Metal) capacitor structure. According to the metal-oxide-metal capacitor structure, by utilization of a symmetric structure, the parasitic inductance and resistance of pole plates at the two ends of the MOM capacitor are effectively reduced, and the application range of the MOM capacitor is expanded; and simultaneously, the structure is used as a unit, and the capacitor with large capacitance is formed by utilizing repeated parallel connection of the unit structures, so that the difficulty in establishing a radio-frequency MOM capacitance model is reduced.

The invention discloses a voltage booster circuit, the development cost and the maintenance cost of which are lower. The voltage booster circuit comprises a switch, and further has a signal generating circuit, wherein the signal generating circuit outputs a pulse signal to control the opening and the closing of the switch. The invention is widely applied to consumption electronic products.

A miniaturized wideband surface mount bias tee comprises a printed circuit board with a functioning first capacitor and a dummy second capacitor, and an inductor bonded atop the two capacitors. The capacitors, adhesive and solder are depositable by standard surface mount pick and place machinery. The inductor wires are bonded to one of the first capacitor bonding pads and to an inductor bonding pad. The circuit element bonding pads include portions bordering the pc board edges and are conductively connected to bonding pads on the bottom face of the pc board. Conductive thru-vias for the first capacitor bonding pads reduce parasitic inductance and extend the operating frequency range. A flat-topped insulating cap encloses the bias tee sides and top. The cap forms an air gap between the inductor and circuit elements and provides a surface for manipulating the bias tee with present-day assembly equipment.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. The invention improves device structure design and finally integrates Schottky contact or heterojunction contact with rectifying characteristics on the basis of traditional silicon carbide UMOSFET structure. At that same time of optimize the basic characteristics of the traditional silicon carbide UMOSFET structure, the improvement realize the integration of multi-sub rectifier devices, greatly optimizes the work performance of the third quadrant of the device, and in addition, the invention also optimizes the dynamic performance of the device, and has shorter switching time; In addition, the invention also has the characteristics of simple process and easy realization.

The invention discloses a SiC power device driving circuit capable of suppressing bridge arm crosstalk and a control method thereof. The driving circuit comprises a G-pole driving circuit, an S-pole driving circuit and a capacitor arranged between the G-pole driving circuit and the S-pole driving circuit. The G-pole drive circuit comprises a positive voltage power supply, a first G-pole switch tube, a second G-pole switch tube, a switch-on resistor and a switch-off resistor, wherein the first G-pole switch tube, the second G-pole switch tube, the switch-on resistor, the switch-off resistor andthe second G-pole switch tube are used for controlling the G-pole voltage state and are sequentially connected in series. The S-pole drive circuit comprises a negative voltage power supply, a first S-pole switch tube and a second S-pole switch tube, wherein the first S-pole switch tube and the second S-pole switch tube control the S-pole voltage state. The negative-voltage power supply, the firstS-pole switch tube and the second S-pole switch tube are sequentially connected in series. According to the invention, the influence of the gate-source parallel capacitor on the switching speed is reduced, and the problem of bridge arm crosstalk is effectively inhibited.

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. Discontinuous gate structures are formed on the basis of the common silicon carbide MOSFET structure, two silicon carbide deep P injection regions are introduced between the two gate structure and metal or polycrystalline silicon is introduced between the two silicon carbide deep P injection regions. The metal or the polycrystalline silicon directly contacts the silicon carbide N-epitaxy so as to form the Schottky contact or the heterojunction contact having the rectification characteristic. The improvement greatly optimizes the conventional silicon carbide UMOSFET basic characteristics, realizes integration of multiple sub-rectifiers and greatly optimizes the third quadrant performance of the device. Meanwhile, the silicon carbide MOSFET device has the characteristics of low Miller capacitance, simple process and easy implementation.

Passive balanced probes are disclosed for use with a signal analysis device. The probes are very low cost relative to typical commercially available probes and provide an extremely flat response over a frequency range of approximately 0 to at least 1.5 gigahertz. The probes include a probe body constructed primarily from conventional components, a first surface mount resistor electrically connected between a probe tip and a center conductor, and two surface mount resistors electrically connected and parallel between the center conductor and a conductive shield. The probes further include a coaxial cable for connection to an instrument combiner or other instrument connection device.

The invention discloses a GaAs PIN diode, which comprises: a semi-insulating GaAs underlay for supporting the whole GaAs diode; a high doped layer N growing in extension on the semi-insulating GaAs underlay, resistive formations I and P close to eigen growing in extension in turn on the high doped layer N; By wet process and etching, the areas of the said high doped layer N, resistive formations I and P reduced in turn to form a mesa structure; a top electrode of the round structure formed by metal evaporator on layer P; a semi-orbicular bottom electrode formed by metal evaporator on layer N. The invention also discloses a manufacturing method of GaAs PIN diode. The invention efficiently lowers the parasitic capacitance of the PIN diode without increasing the difficulty of the process and simultaneously greatly shortens the microstrip line connected with the top electrode. The spurious inductance brought by the invention can be greatly reduced or even omitted without using the air-bridge process. The invention has the advantages of easy making, better high frequency characteristic, which is easy to realize the single scale integration.

The invention discloses a double-surface heat-dissipation and high-reliability power module. The double-surface heat-dissipation and high-reliability power module comprises a positive power terminal, a negative power terminal, an output power terminal, a bottom metal insulating substrate and a top metal insulating substrate; the bottom metal insulating substrate and the top metal insulating substrate are laminated; an output local metal layer is arranged on the bottom metal insulating substrate or the top metal insulating substrate; the output power terminal is connected to a chip connection block through the output local metal layer; and the chip connection block is electrically connected with a chip on the bottom metal insulating substrate and a chip on the top metal insulating substrate. By means of the double-surface heat-dissipation and high-reliability power module disclosed by the invention, the loop parasitic inductance is greatly reduced; interconnection is realized by adoption of a material matched with the thermal expansion coefficient of the chip; the cracking risk of a welding layer can be reduced; the reliability of the power module can be improved; the volume of the power module is reduced; the cost is reduced; the weight is lightened; the module is particularly suitable for encapsulation of a SiC power chip; and thus, the discharge capacity is sufficiently improved.