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Low-parasitic-inductance GaN power integration module arranged in middle of shunt capacitor

A technology of low parasitic inductance and power integration, applied in high-efficiency power electronic conversion, output power conversion devices, circuits, etc., to avoid oscillation and spikes, reduce parasitic inductance, and reduce parasitic inductance

Active Publication Date: 2014-11-12
XI AN JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the parasitic oscillation phenomenon still exists, and it is necessary to further optimize the layout and wiring methods to reduce the high-frequency power loop inductance

Method used

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  • Low-parasitic-inductance GaN power integration module arranged in middle of shunt capacitor
  • Low-parasitic-inductance GaN power integration module arranged in middle of shunt capacitor
  • Low-parasitic-inductance GaN power integration module arranged in middle of shunt capacitor

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0021] In the GaN power integrated module of the present invention, the upper bridge arm device 1, the lower bridge arm device 2 and the bus capacitor 3 are sequentially connected to form a high frequency power circuit 10, the upper bridge arm device 1 and the lower bridge arm device 2 are placed in parallel and side by side, and the bus capacitor 3 is placed between the upper bridge arm device 1 and the lower bridge arm device 2; all the drains of the upper bridge arm device 1 are connected to one electrode of the bus capacitor 3 on the side close to the bus capacitor, and all the sources of the lower bridge arm device 2 are near The bus capacitor side is connected to the other electrode of the bus capacitor 3; all sources of the upper bridge arm device 1 are connected to the middle conductive layer 6 through vias, and all drains of the lower bridge arm...

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Abstract

The invention provides a low-parasitic-inductance GaN power integration module arranged in the middle of a shunt capacitor. The module comprises an upper bridge arm device, a lower bridge arm device and a plurality of bus capacitors. The upper bridge arm device and the lower bridge arm device are LGA packaged GaN devices. The bus capacitors are surface mount devices. The two GaN devices are arranged side by side. The bus capacitors are placed between the two GaN devices in parallel. All source electrode pins of the upper bridge arm device and all drain electrode pins of the lower bridge arm deice are connected to an inner conducting layer through via holes. According to the layout way, the area of a high-frequency power loop can be effectively reduced, so that the parasitic inductance of the high-frequency power loop is obviously reduced, and the overvoltage and oscillation produced in the switching process are reduced.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a low parasitic inductance GaN power integration module arranged in the middle of parallel capacitors. Background technique [0002] GaN power devices are popular new material devices that have appeared in recent years and have been gradually commercialized. Compared with Si devices, they have superior on-state characteristics and very good switching characteristics, so they have attracted the attention of the industry in a relatively short period of time. , Scholars engaged in applied research have also carried out a lot of research work, applying it to low-voltage, low-power power supply devices such as POL and DC / DC. Studies have shown that replacing Si devices with GaN devices can greatly increase the switching frequency while maintaining good efficiency indicators. Undoubtedly, in low-voltage and low-power applications, GaN devices will be more and mor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/07H02M1/00
CPCY02B70/10
Inventor 王康平杨旭曾翔君马焕余小玲郭义宣
Owner XI AN JIAOTONG UNIV
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