49results about How to "Minimize capacitance" patented technology

A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode (134) is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion (137) of the body tie access region. The gate electrode is formed having a substantially constant gate length (88) along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes (98,100) are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion (130) is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.

A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).

A display substrate includes a data line disposed on a base substrate, a first pixel electrode disposed at a first side of the data line, a second pixel electrode disposed at a second side of the data line and a storage electrode overlapping with the data line. The storage electrode overlaps with the first pixel electrode by a first overlapping width, and overlaps with the second pixel electrode by a second overlapping width larger than the first overlapping width.

A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to N^th intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to N^th intermediate metal layers are serially connected. Accordingly, the pad reduces total parasitic capacitance components by connecting MIM type capacitors in series, and not necessarily overlapping with each other, thereby minimizing design errors attributed to the pad by reducing parasitic factors generated from the integrated circuit design. The pad may also minimize capacitance attributed to resonance at a specific frequency. Moreover, the pad avoids affecting an adjacent pad or circuit without additional processing, despite maintaining the above-mentioned effects, thereby reducing cost.

A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).

The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect.

Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

A pulse transformer for use in a high frequency motor controller to isolate the electronic control stages from the power stages in a motor controller. The primary and secondary windings are wound on a common ferrite core and spaced apart from one another. The wire size used for the windings is relatively small (gauge 37 or less). Each of the windings has between 10 and 13 turns. The interwinding capacitance must be below 5 picofarads, preferably below 1 picofarad, and most preferably below 0.2 picofarads.

With a variable capacitor including a load capacitor of an oscillation circuit having a feedback resistor 1, an inverter 2, and a crystal oscillator 3, and a static capacitance generated between a drain terminal and a gate terminal of MOS transistors 4 and 5, in which source and backgate terminals are shorted to each other, a serial connection of a DC cut capacitor 9, 10 and a variable capacitors (MOS transistor) 4 and 5 is formed between one end and the other end of the crystal oscillator 3. For example, a threshold voltage control signal of the MOS transistors 4 and 5 is input to the drain terminal through a high-frequency elimination resistor 11, 12, and is input to the source-backgate terminal through a high-frequency elimination resistor 7, 8. In addition, a signal obtained by overlapping a temperature characteristic compensation signal and a threshold voltage control signal of the MOS transistor 4, 5 is input to the gate terminal. Accordingly, it is possible to indiscriminately determine an output bias of a temperature compensation control circuit or an external voltage frequency control circuit.

The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator (2) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis (25) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector (3) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (17). The illumination system emits light with a uniform spatial and spatio-angular color distribution.

A bipolar semiconductor overvoltage protection circuit presents less capacitance to a communication line. The overvoltage protection circuit includes an overvoltage protection device that is biased with a voltage to not only reduce the capacitance thereof, but also to reduce the change in capacitance as a function of frequency. Changes in communication line voltages thus change the capacitance of the overvoltage protection device less, resulting in the ability to allow the transmission of high capacity data protocols with reduced error rates.

A metal line layout which includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting Werner Fill processing. One control space (i.e., DRCgap₁) is for decreasing the spacing between various metal features to standardize such spacing, and a second control space (i.e., DRCgap₂) is for addressing capacitance issues along speed sensitive pathways. Between speed sensitive pathways, spacing of added metal features provided to long parallel metal lines are maintained at the second control spacing DRCgap₂. Spaces at the ends of such long parallel metal lines are reduced to the first control spacing DRCgap₁ in order to best fill three-way-intersections (TWIs) with subsequent depositions.