14results about How to "Reduce overlap area" patented technology

The invention discloses an interleaved parallel flyback micro inverter control method and device, and a readable medium. The method comprises the steps of obtaining a direct current voltage and a direct current of a photovoltaic module at an input end of a micro inverter, and performing maximum power point tracking calculation to obtain a reference output power; obtaining a power grid voltage instantaneous value and carrying out effective value calculation to obtain a power grid voltage effective value; calculating a grid-connected reference current effective value according to the reference output power and the grid voltage effective value; by setting a secondary side current overlapping factor and calculating and adjusting the switching frequency and the duty ratio, a secondary side current overlapping area is reduced to the greatest extent, and the peak value of the secondary side current can be reduced as far as possible, so that the current stress of a flyback diode and a power frequency flip circuit switching tube is reduced, and the grid-connected current quality is improved.

The invention provides a thin film transistor and a preparation method thereof, an array substrate, a display panel and a display device. The thin film transistor comprises a substrate, a first electrode, a first insulating layer, a second electrode, an active layer, a second insulating layer and a control electrode. The first pole is arranged on one side of the substrate, the first insulating layer is arranged on one side, away from the substrate, of the first pole and comprises a first hole, the first pole is at least partially exposed in the first hole, and the second pole is arranged on one side, away from the substrate, of the first insulating layer. The active layer is arranged on the sides, away from the substrate, of the first electrode and the second electrode and connected between the first electrode and the second electrode, the active layer is partially attached to the side wall of the first hole in the circumferential direction of the first hole, and the second insulating layer is arranged on the side, away from the substrate, of the active layer and partially attached to the side wall of the first hole. The control electrode is arranged on the side, away from the substrate, of the second insulating layer. And the orthographic projection part of the second pole on the substrate surrounds the orthographic projection of the first hole on the substrate.

The invention discloses a display panel and a display device. The display panel comprises a substrate and at least two signal wiring layers located on one side of the substrate. A first signal wire extending along a first direction and a second signal wire extending along a second direction are arranged in the at least two signal wire layers, and the first signal wire and the second signal wire are located in different signal wire layers; the first signal wire is connected with at least one second signal wire through a via hole; the first signal wire and the second signal wire respectively comprise a connecting part at the via hole position, and respectively comprise an overlapping part at the non-via hole overlapping position; in the first signal line, the size of the overlapping part is smaller than that of the connecting part in the second direction; and / or, in the second signal wire, the size of the overlapping part is smaller than that of the connecting part in the first direction. According to the technical scheme, the coupling capacitance is reduced, and the display mura problem of the display area is improved.

The application discloses a semiconductor device and a manufacturing method thereof, and a storage system. The semiconductor device comprises a channel structure, a capacitor structure, a bit line and a word line. The channel structure extends along a first direction. The bit line and the capacitor structure are connected to two ends of the channel structure along the first direction respectively. The word line comprises a word line part and a unidirectional conduction part which are connected to each other, and the word line part and the unidirectional conduction part cover at least part of the channel structure respectively.

The utility model discloses a compound fish scale tile, which relates to the field of building roof materials, and comprises a fish scale tile body and a main water guide side groove which are integrally formed, the fish scale tile body comprises a lap joint part and a modeling part, the modeling part comprises a plurality of rows of fish scale modeling plates which are arranged in a stacked mode, and more than two fish scale modeling plates are arranged in each row. The scale-shaped plates are arranged in the same row, every two adjacent rows of scale-shaped plates are arranged in a staggered mode, a water guiding ditch is formed between every two scale-shaped plates in the same row, and the main water guiding edge grooves are formed in the side edge of one side of the scale-shaped tile body. The side edge of one compound scale tile is in lap joint with the main water guiding edge grooves of the adjacent compound scale tiles when multiple compound scale tiles in the same row are laid; when the compound scale tiles in different rows are laid, the modeling parts of the compound scale tiles in the upper row are in lap joint with the lap joint parts of the compound scale tiles in the next row. While the appearance effect is ensured, the number of tiles and the overlapping area of the tiles are greatly reduced, the construction efficiency is improved, the use cost is reduced, and the weight of a roof is reduced.

The application relates to the technical field of shock absorbers, and discloses a light-weight high-strength motorcycle shock absorber which comprises a connecting cylinder, a nut plate one is threadedly connected to the outer wall of the connecting cylinder, a spring one is fixedly connected to the top of the nut plate one, and the device will appear hard bottom impact when bearing huge impact; the slide rod bears pressure and drives the piston to quickly move downwards along the inner wall of the connecting cylinder; the bottom sharp corner of the supporting plate will first contact the groove at the bottom of the connecting cylinder; after the sharp corner is limited, the piston continues to move downwards and forces the supporting plate to push the fixed plate to slide along the sliding groove through the universal joint, forces the feeding port one to be dislocated with the feeding port three, and the overlapping area of the two is reduced, which will reduce the cross section of the flow aperture, increases the sliding resistance of the piston before hard bottom, and reduces the fatigue loss of the related components caused by hard bottom.

This application provides a display panel and a display device aimed at improving antenna performance. The display panel includes: a support layer comprising a conductive material; and an antenna layer disposed on one side of the support layer in the thickness direction of the display panel, the antenna layer including an antenna element; wherein the support layer includes a through gap, and the projection of the antenna element in the thickness direction and the projection of the gap in the thickness direction at least partially overlap.

The invention discloses a VLSI (Very Large Scale Integration) mixing unit collaborative layout method based on evolutionary knowledge and landscape perception, aiming at the defect that the prior art depends on static Netlist information and cannot perceive and optimize dynamic coupling of landscape. The method comprises the following steps: extracting four-dimensional evolution knowledge characteristics of convergence time, an accumulation path, symbol flipping times and direction consistency of a module through a preview stage, constructing a landscape perception type component neighborhood based on clustering analysis, and realizing normal form transformation from structure correlation degree to behavior correlation degree. The method comprises the specific steps that S1, knowledge-driven component neighborhood construction and rehearsal population generation are carried out, and dynamic grouping is generated through initial population legalization, rehearsal behavior data accumulation, feature extraction and clustering; s2, two-stage collaborative optimization of knowledge solidification: firstly optimizing a macro cell group and freezing coordinates, and then optimizing a standard cell group and introducing hot area search; and S3, performing mixed overlapping typing detection and cost evaluation, calculating three types of overlapping areas through hierarchical detection, and constructing a total cost function. According to the method, the implicit coupling relation is effectively captured, the grouping accuracy and optimization efficiency are improved, the zero-overlapping and low-HPWL targets are achieved, and the method is suitable for a high-dimensional noise-containing VLSI layout scene.

A heater arrangement for an apparatus for layer-by-layer formation of a three-dimensional object by the consolidation of particulate matter, the heater arrangement having a heater arrangement area, and comprising: one or more shrouded radiative heating elements, arranged over the heater arrangement area, the shrouded radiative heating elements being operable to heat particulate matter at a build bed surface of said apparatus to a desired temperature profile; and one or more radiation-restricting shrouds, which are arranged in communication with the shrouded radiative heating elements, and each of which form one or more passages for restricting the solid angle over which radiation is emitted by the shrouded radiative elements, each passage having a first end which opens towards at least one of said shrouded radiative heating elements, and a second end which opens to the exterior. Also provided is apparatus for layer-by-layer formation of a three-dimensional object by the consolidation of particulate matter, the apparatus comprising: a working space having opposing bottom and top sides; a build bed surface on said bottom side of the working space and upon which successive layers of said object are formed, the build bed surface comprising a printable area; and a heater arrangement area on said top side of the working space and comprising a plurality of spaced-apart radiative heating elements arranged on said top side of the working space, the radiative heating elements being operable to heat particulate matter at the build bed surface to a desired temperature profile; wherein said plurality of spaced-apart radiative heating elements comprises a first group of four or more radiative heating elements; and wherein, as viewed from said top side of the working space, said first group of four or more spaced-apart heating elements is arranged beyond and around the perimeter of printable area and within the heater arrangement area.

The invention discloses a display panel and a display device, and relates to the technical field of display, the display panel comprises a substrate, an active layer located on one side of the substrate and multiple metal layers located on the side, away from the substrate, of the active layer, and the multiple metal layers comprise the first metal layer and the second metal layer; the display panel comprises a first shielding area, and at least part of an active layer is located in the first shielding area; the first shielding area is arranged in the direction perpendicular to the plane where the substrate base plate is located, and at least one of the entity part of the first metal layer and the entity part of the second metal layer covers the first shielding area, so that the active layer in the first shielding area is covered, and the active layer in the first shielding area is prevented from being affected when a light emitting diode is bonded through laser; and meanwhile, a plurality of openings are formed in the first metal layer, and a plurality of openings are formed in the second metal layer, so that the areas of the entity part of the first metal layer and the entity part of the second metal layer are reduced, the overlapping area of the two is reduced, and the short-circuit risk of the two is reduced.

The utility model relates to a flange structure of a mine underground supporting anchor net, which comprises a bending component and a driving component which are distributed on two sides and are oppositely arranged, the bending component comprises two groups of bending machines which are opposite in bending direction and are arranged on one side at intervals, so that adjacent flanges on the same side of the formed supporting anchor net are opposite, and the bending direction of the bending machines is opposite to that of the driving component. The net sheet structure of the supporting anchor net is stable and is not easy to loosen; the bending directions of the opposite bending machines are opposite, it is guaranteed that the bending directions of the left end and the right end of the supporting anchor net are opposite, when the mine underground supporting anchor net is spliced, hanging splicing of the adjacent supporting anchor nets is facilitated, the overlapping area is saved, and meanwhile forward and reverse staggering of the splicing position structure is firmer; the driving assembly comprises a sliding rail extending towards the two sides, a driving base and a driving piece, the bending assembly is arranged on the driving base, the driving base is arranged on the sliding rail in a sliding mode, and the driving piece is connected with the driving base and enables the driving base to do linear translation reciprocating motion. The whole structure can be used along with a production line of the supporting anchor net in a matched mode, and the edge bending efficiency of the supporting anchor net is improved.

The application discloses a display panel, a preparation method thereof and a display device. The array substrate of the display panel comprises a plurality of heating wires and a plurality of first display signal lines which are arranged in different layers and cross each other. The heating wire comprises a first section and a second section arranged along a first direction. The vertical projection of the second section on a substrate is overlapped with the vertical projection of the first display signal line on the substrate. The area of the second section per unit length is smaller than the area of the first section per unit length along the first direction. The display panel, the preparation method thereof and the display device provided by the application reduce the area of the overlapped part of the heating wire and the first display signal line, reduce the parasitic capacitance formed between the heating wire and the first display signal line and the coupling power consumption, and improve the display effect and display performance of the display panel at low temperature under lower power consumption.

The invention discloses a metal oxide semiconductor field effect transistor and a preparation method thereof. Each cell in the metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a current expansion layer, a base region layer, an injection layer, a source metal region and a gate region, the drain metal layer, the substrate, the epitaxial layer, the current expansion layer, the base region layer and the injection layer are stacked in sequence; the upper part of the source electrode metal region covers the injection layer and the upper surface of the gate region, and the lower part of the source electrode metal region penetrates through the injection layer, the base region layer and the current expansion layer and extends to a buried layer region in the epitaxial layer; the side wall of the source metal region comprises a Schottky contact region and a gate region with the side wall as a longitudinal center line. According to the embodiment of the invention, the dynamic characteristics of the metal oxide semiconductor field effect transistor are improved while the conduction voltage drop and the reliability of the silicon carbide metal oxide semiconductor field effect transistor are ensured.