224results about How to "Reduce overlap area" patented technology

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

A four color liquid crystal display (LCD) including red, green, blue, and white sub-pixels are provided. The LCD also includes a plurality of gate lines for transmitting gate signals to the sub-pixels and a plurality of data lines for transmitting data signals to the sub-pixels. The white sub-pixel is smaller than the other sub-pixels, and each of the data lines passes between adjacent two sub-pixels and includes at least one curved portion. Furthermore, the lengths of the data lines are substantially uniform.

The invention discloses a structure for a touch control device and a touch control display panel. The touch control device comprises a patterned sensing electrode structure, an insulating layer and a patterned sharing electrode layer. The patterned sensing electrode structure is arranged on the surface of a substrate defined with a plurality of display areas and a shading area, wherein the display areas are exposed corresponding to the shading area. The insulating layer covers the patterned sensing electrode structure. The patterned sharing electrode layer is arranged on the surface of the insulating layer, and comprises a plurality of electrode parts corresponding to the display areas and a plurality of connecting parts arranged between adjacent electrode parts and electrically connected to the electrode parts. The touch control device provides the patterned sensing electrode structure corresponding to the shade area, coordinately provides the electrode parts of the patterned sharing electrode layer corresponding to the display areas, and reduces area of the connecting parts to reduce superposition area of the patterned sensing electrode structure and the patterned sharing electrode layer, so as to reduce coupling capacitance thereof and promote intensity of sensed signals sensed by the patterned sensing electrode structure.

There is provided a tape recording system and head device. A tape recording system and head device include a plurality of recording sections for recording data signals on a recording medium wherein one recording section of the plurality of recording sections and another recording section arranged so as to adjoin the one recording section are disposed such that the one recording section and the another recording section are shifted from each other in a running direction and a width direction of the recording medium, and wherein the one recording section and another recording section simultaneously record a data signal on adjacent recording tracks on the recording medium.

A thin film transistor (TFT) that comprises a gate electrode on a substrate, a gate insulation layer on the gate electrode, an active layer having a source region, a drain region, and a channel region on the gate insulation layer, and a source electrode and a drain electrode formed over the source region and drain region of the active layer respectively and facing each other with respect to the channel region. The profile of channel region between the source electrode and drain electrode is changed in a bend line. A method for forming the TFT is also provided.

The invention relates to a structured light quick scanning microscopic imaging method. The method comprises the following steps of: (1) controlling a spatial light modulator to generate a modulation pattern with single spatial frequency by a computer, and projecting the modulation pattern on a sample fracture; (2) under the condition that the phase of the modulation pattern is unchanged, driving a sample to move by an electric control movement platform, and synchronously triggering a line-scan digital camera to take a picture; (3) changing the phase of the modulation pattern, and scanning the same imaging region until different lighting phase images required by structured light imaging is acquired; and (4) moving a sample, and executing the steps (2) to (4) for the subsequent adjacent imaging region until the whole sample fracture is scanned. By performing phase change for one time before scanning motion is performed at each time, requirements of imaging on the speed and robustness of the modulator are reduced; and in single-time scanning motion, a complete image is acquired, and adjacent images are partially overlapped. Sample motion and camera exposure are synchronously performed, so that time is saved, and imaging speed is increased.

The invention relates to the field of liquid crystal display and particularly relates to an array base plate, a manufacturing method thereof and a liquid crystal display device which are used for solving the problems of large grid electrode size and increased feed-in voltage value in the prior art. The array base plate provided by the embodiment of the invention comprises a thin film transistor arranged on a substrate base plate, a grid line connected with the thin film transistor and a shielding layer positioned between the substrate base layer and an active layer of the thin film transistor; the shielding layer is used for shielding light rays injected into the active layer; and the line width of a grid electrode is less than that of the grid line in which the grid electrode is positioned. According to the embodiment of the invention, the shielding layer shields the light rays injected into the active layer, and the line width of the grid electrode is less than that of the grid line in which the grid electrode is positioned, so that the value of the interelectrode capacitance of a TFT (Thin Film Transistor) is reduced, and further feed-in voltages influencing the frame level of a TFT-LCD (Liquid Crystal Display) can be reduced.

This invention discloses a TFT LCD array base plate structure including: a base plate, a grid, grid scanning lines and a public electrode, in which, the public electrode is a base electrode of the storage capacitance, a grid insulation layer, an active layer and a channel on it, a data scanning line, source and drain, a top electrode of the storage capacitor formed above the grid insulation layer, a passivation layer and its through hole or groove formed above the drain and the storage capacitor top electrode, pixel electrode formed on the passivation layer and connected with the drain and the top electrode of the storage capacitor via the passivation layer through hole or groove. This invention also discloses a manufacturing method for said array base plate structure, which can reduce the area of light strips and the overlapped area between the light strip and pixel electrode, the publick electrode and the transparent electrode so as to increase the open-end rate and storage capacitance.

The invention provides an array substrate and a display device. The array substrate includes a shift register, a plurality of signal lines and a plurality of transmission lines, wherein the extending direction of the signal lines intersects with that of the transmission lines, and the signal lines and the transmission lines are located at different layers; one end of each transmission line is electrically connected with the corresponding signal line, and the other end of each transmission line is electrically connected to the corresponding input end of the shift register; for any transmission line, when other signal lines exist between the signal line connected with the transmission line and the shift register, at least one signal line between the signal line connected with the transmission line and the shift register is provided with a first through hole; the first through hole is positioned at the overlap area between the signal line and the transmission line. According to the invention, the overlap area between the transmission line and the signal line is reduced to decrease the signal delay, realize consistence of the delays of different signal lines, and improve the display effect of the display device.

The present invention relates to the micro inertial navigation technology related field, particularly to a high Q value micro-machined gyroscope structure based on nanometer grating detection, wherein the micro-machined gyroscope structure is provided with a boss provided with a fixed nanometer grating, and with the boss, the overlapping area between the lower layer fixed structure and the upper layer movable structure can be reduced. According to the present invention, the lower layer fixed grating is arranged on the boss so as to reduce the overlapping area between the lower layer fixed structure and the upper layer movable structure; when the mass block of the micro-machined gyroscope produces the horizontal displacement under the effect of Coriolis force, the slide film damping coefficient between the upper layer structure and the lower layer structure is substantially reduced, such that the sensitivity of the micro-machined gyroscope structure is increased, wherein the structure sensitivity of the micro-machined gyroscope based on the nanometer grating detection is increased by 1-2 orders of magnitude; and the whole structure is compact, and the structure has the high sensitivity.

The invention discloses a method for optimizing the coverage of nodes of a wireless sensor network. The method is characterized in that the coverage of the nodes of the wireless sensor network is defined as a discretization plane geometry problem, wireless sensors are idealized into standard circles with radiuses within a communication range, the circles are overlapped, centers of the circles are constrained, and then the circles are optimized by an evolution mechanism of a differential evolution algorithm. Overlapped areas among the sensors need to be reduced in order to increase a regional coverage rate, and the coverage capacity of the sensors can be efficiently utilized in a non-overlapping manner. The method has the advantages that the sensors are rearranged when the quantity of the overlapped sensors is excessively high, and an experiential threshold overlapping value (for example, an optimization effect is realized when 20-40 wireless sensors are distributed in 100X100 monitored regions and the threshold overlapping value n is equal to 6) can be obtained after repeated experimental comparison.

An X-ray detector including a thin film transistor (TFT) substrate and a photo-diode array layer is disclosed. Each thin film transistor in the TFT substrate includes: a substrate; a gate-electrode on the substrate; a gate insulating layer on the gate-electrode; a semiconductor layer on the gate insulating layer, wherein a portion of the semiconductor layer covers the gate-electrode; an etching stop layer covering the semiconductor layer; a source-electrode and a drain-electrode respectively disposed on the etching stop layer, wherein the source-electrode and the drain-electrode are respectively electrically connected to the semiconductor layer through conductive via-holes each having a base portion at the semiconductor layer, and at least one of the projection areas of the base portions vertically projected on the substrate has a non-overlapping region beyond the projection area of the gate-electrode vertically projected on the substrate; and a passivation layer covering the source-electrode and the drain-electrode.

This invention discloses one MOS field effect tube and its process method, which has side wall bottom concaved toward inside. The field effect tube method comprises the following steps: a, injecting well ions for annealing to sacrifice oxidation layer peeling off; b, growing or depositing one layer of thick oxidation layer; c, processing total etching in middle area oxidation; d, growing grating oxidation; e, depositing multiple transistor grating; f, processing light etch on thick oxidation area; g, regular steps after etching.

One embodiment of the invention provides a thin film transistor and a preparation method thereof, an array substrate and a display device, and relates to the technical field of display, reducing the self-stray capacitance of the TFT. The thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein a first opening part is formed on the grid electrode/or the source electrode, and the first opening part is positioned at least at an overlapping area of the grid electrode and the source electrode; an/or, a second opening part is formed on the grid and / or the drain electrode, and the second opening part is positioned at least at the overlapping area of the grid electrode and the drain electrode.

A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region.

The invention discloses an array substrate, a manufacturing method therefore, and a display panel. The array substrate includes a plurality of thin film transistor, and each thin film transistor comprises a gate electrode, an oxide semiconductor layer, and an etching barrier layer, wherein the etching barrier layer is located on the oxide semiconductor layer which includes a channel region and a non-channel region, the non-channel region includes an electrode region and a connection region, and the electrode region includes a first electrode region and a second electrode region. Each connection region includes a first connection region and a second connection region, and the first electrode region, the first connection region, the channel region, the second connection region and the secondelectrode region are sequentially arranged in a first direction, and the first direction is parallel to the array substrate. A region, covered by the corresponding etching barrier layer, of each oxide semiconductor layer is a channel region. Each gate electrode is located at one side, far from the corresponding etching barrier layer, of the corresponding oxide semiconductor layer. The width of atleast one connection region is less than the width of the channel region in a second direction. The overlapping area of the gate electrodes with the non-channel regions is reduced, and the parasiticcapacitance is also reduced.

The invention relates to a semiconductor structure capable of reducing a switching loss and a manufacturing method. A drain electrode, a first conductive type substrate and a first conductive type epitaxial layer are sequentially arranged in a stacked mode from bottom to top; a plurality of second conductive type body regions are formed in the first conductive type epitaxial layer, the plurality of second conductive type body regions are distributed at intervals; heavily doping is performed in the second conductive type body regions to form a first conductive type second source region, and heavily doping is performed in the second conductive type body regions on one side of the first conductive type second source region to form a first conductive type first source region; a control gate structure is arranged between the first conductive type first source region and the first conductive type second source region which are adjacent to each other; a virtual gate structure is arranged on one side, far away from the first conductive type first source region, of the first conductive type second source region; an insulating dielectric layer is deposited on an upper surface of the semiconductor structure for reducing the switching loss; and at a middle position of the first conductive type first source region, a connecting hole is formed downwards from the upper surface of the insulating dielectric layer, and the connecting hole extends downwards into the first conductive type first source region.

Deterioration of image quality in a display device due to kickback voltages may be reduced or prevented by varying parasite capacitance, the size of the semiconductor layer, and/or storage capacitance in each of thin film transistors for the pixels in the display. Various embodiments of display devices capable of reducing or preventing kickback voltages are disclosed.

A touch panel including a substrate and a sensing array is provided. The sensing array is disposed on the substrate and includes a plurality of sensing units. Each sensing unit has a first sensing electrode and a second sensing electrode which are arranged in a staggered manner and are electrically insulated from each other. The first sensing electrode includes two parallel first sensing pads and a first connection portion. The second sensing electrode includes two parallel second sensing pads and a second connection portion. The first sensing pads, the first connection portion, the second sensing pads, and the second connection portion are in rectangular shapes, and short sides of the first connection portion and the second connection portion are electrically connected to middle portions of long sides of the first sensing pads and the second sensing pads respectively. The second connection portion and the first connection portion intersect each other.

The invention discloses an array substrate, a display panel and a preparation method of the array substrate. The array substrate comprises a thin film transistor and a capacitor, and the capacitor comprises a first electrode layer, a first insulating layer and a second electrode layer which are arranged on a substrate; the orthographic projection area of the first electrode layer is a first area,and the orthographic projection area of the second electrode layer is a second area; an overlapping region of the orthographic projection regions of the first electrode layer, the first insulating layer and the second electrode layer forms a capacitor, the width of the second area is a first width, the width of the first area except the second area is a second width, and the first width is largerthan the second width.