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Array substrate and display device

An array substrate and overlapping area technology, applied in optics, instruments, electrical components, etc., can solve problems such as large capacitance value, and achieve the effect of reducing capacitance value and reducing overlapping area

Inactive Publication Date: 2015-01-07
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Embodiments of the present invention provide an array substrate and a display device to solve the C gc and / or C dc The problem of relatively large capacitance value

Method used

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  • Array substrate and display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0074] The solution of the embodiment of the present invention will be described below by taking the structure of a pixel unit included in the array substrate in the HADS mode display device as an example.

[0075] Such as figure 2 As shown, the array substrate of the HADS mode display device includes: a gate line 10 and a data line 20 crossing each other to define a pixel unit, a TFT (thin film transistor) 30 and a pixel electrode 40 located in the pixel unit and electrically connected to each other, and A common electrode line 50 that is provided on the same layer as the gate line 10 and is insulated from each other, and a common electrode layer 70 that is electrically connected to the common electrode line 50 through a via hole 60;

[0076] There is an overlapping area A between the electrically insulated common electrode layer 70 and the gate line 10, and an overlapping area B exists between the electrically insulated common electrode layer 70 and the data line 20;

[00...

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Abstract

The invention relates to the display technology field, in particular to an array substrate and a display device. The array substrate and the display device are used to solve the problem that Cgc and / or Cdc capacitance is large in the prior art. The array substrate comprises a grid line, a data line and a common electrode layer which is electrically insulated from the grid line and the data line, wherein at least one overlapping area exists between the common electrode layer and the grid line, and / or, at least one overlapping area exists between the common electrode layer and the data line, and furthermore the common electrode layer comprise hollow structure portions located on the at least one overlapping area, and each hollow structure portion located on the at least one overlapping area comprises at least one hollow area. The array substrate and the display device can decrease the Cgc and / or the Cdc capacitance.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate and a display device. Background technique [0002] When the array substrate not only includes gate lines and data lines, but also includes a common electrode layer electrically insulated from the gate lines and data lines, a parasitic capacitance C will be formed between the common electrode layer and the gate lines gc , and a parasitic capacitance C will be formed between the common electrode layer and the data line dc . [0003] At present, there may or may not be an overlapping area between the electrically insulated common electrode layer and the gate line; wherein, when there is an overlapping area between the common electrode layer and the gate line, C gc The capacitance value is relatively large. Similarly, when there is an overlapping area between the electrically insulated common electrode layer and the data line, C dc The capacitance val...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1343G02F1/1333H01L27/32G02F1/167
CPCG02F1/136286G02F1/13606H01L27/1214H01L27/1248G02F1/133345G02F1/134309G02F1/134363G02F1/136G02F2201/121G02F1/134318G02F1/134372G02F1/134381H01L27/124
Inventor 宁策吴俊纬张玉婷
Owner BOE TECH GRP CO LTD
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