20results about How to "Reduce coupling capacitance" patented technology

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; a plurality of first isolation grooves and a plurality of second isolation grooves are formed in the substrate, the first isolation grooves extend in the first direction, the second isolation grooves extend in the second direction, and the first direction and the second direction are parallel to the substrate and intersect with each other; the plurality of first isolation grooves and the plurality of second isolation grooves jointly isolate a plurality of active columns arranged in an array. The plurality of active columns are arranged in a row along a first direction; a plurality of bit lines arranged at intervals; the bit lines are located below the active columns and extend in the first direction, and the active columns located in the same row are sequentially connected in series; a plurality of air gap structures; the air gap structures are located between the adjacent bit lines and located at the bottoms of the corresponding first isolation grooves. The semiconductor structure can improve the read-write speed of the memory, so that the memory has more excellent electrical performance.

A semiconductor device and a method for preparing the semiconductor device, the semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bit line connection line and a second bit line connection line, the first semiconductor structure comprises a sensing amplifier circuit, the second semiconductor structure is connected to the first semiconductor structure by bonding and comprises a first storage unit, the third semiconductor structure is connected to the second semiconductor structure by bonding and comprises a second storage unit, the first bit line connection line is associated with the first storage unit, the second bit line connection line is associated with the second storage unit, the first bit line connection line and the second bit line connection line are comparatively coupled to each other by the sensing amplifier circuit, and the length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns. The coupling capacitance of adjacent bit lines can be reduced, the anti-crosstalk capability can be improved, and the difference in signal transmission time delay can be reduced, thereby improving the stability and reliability of the device.

The invention discloses a display panel and a display device. A pixel driving circuit of the display panel comprises a switch transistor, a driving transistor, a first light-emitting transistor and a first reset crystal which are connected to a first node, a grid electrode of the first light-emitting transistor is connected to a light-emitting control line, a conductive section of an area where the first node is located is located on an active layer, and the light-emitting control line is located on a first source-drain electrode layer. The conductive section and the light-emitting control line have an overlapped part; the conductive section of the area where the first node is located is located on the active layer, and the light-emitting control line is located on the first source-drain electrode layer, so that the conductive section is replaced by a conductor semiconductor layer from a metal layer, the distance between the light-emitting control line and the conductive section is increased, the coupling capacitance between the light-emitting control line and the first node is reduced, and the light-emitting efficiency is improved. The abnormality of the potential of the first node is improved, and the display effect of the display panel is improved.

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for improving the brightness uniformity of the display panel. The display panel comprises a substrate, a data line and a pixel driving circuit, wherein the data line and the pixel driving circuit are located on one side of the substrate; the pixel driving circuit comprises a driving transistor, a bias adjusting transistor and a first connecting part, a grid electrode of the driving transistor is electrically connected with the first node, a first pole of the driving transistor is electrically connected with the second node, and a second pole of the driving transistor is electrically connected with the third node; the first connecting part is electrically connected with the bias adjusting transistor and the second node; the display panel further comprises a first semiconductor layer and a first metal layer, and the first semiconductor layer and the first metal layer are sequentially stacked in the direction away from the substrate. The first semiconductor layer comprises a channel of the driving transistor and a channel of the bias adjusting transistor, and the first metal layer comprises a grid electrode of the driving transistor and a grid electrode of the bias adjusting transistor; the first connection member is located on the first semiconductor layer.

The invention provides a semiconductor device and a preparation method thereof, and a memory system. The semiconductor device comprises a plurality of silicon columns arranged in an array; the oxidation insulating layer is arranged between any two adjacent silicon columns; the bit lines are arranged on one side of the silicon column; according to the semiconductor device provided by the invention, an isolation structure used for reducing coupling capacitance can be formed on the oxidation insulating layer between two adjacent bit lines, and the first insulating layer is arranged on the side, deviating from the silicon column, of the bit lines, so that the isolation structure can be used for reducing the coupling capacitance, and the isolation structure can be used for reducing the coupling capacitance. According to the semiconductor device, the gap between the first insulating layers arranged on the sides, away from the silicon column, of the two adjacent bit lines can be further utilized, so that the arrangement space of the isolation structure is increased, the coupling capacitance between the bit lines is reduced, the sensing tolerance of the semiconductor device is improved, and the performance of the device is improved.

The invention provides a display panel and a display device, and relates to the technical field of display, a pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, a grid electrode of the driving transistor is connected with a first node, a first pole is connected with a second node, and a second pole is connected with a third node; two ends of the first reset module are respectively connected with a first reset signal line and a first node, and a control end is connected with a first scanning line; two ends of the data write-in module are respectively connected with a data signal line and a second node, and a control end is connected with a second scanning line; the display area comprises a first display area and a second display area which are arranged in the first direction, and the first display area is located between the second display area and the binding area; in each pixel driving circuit, a first capacitor is formed between the first node and the second scanning line; the capacitance value of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance value of the first capacitor in the pixel driving circuit corresponding to the second display area, so that the display uniformity is improved.

The embodiments of the present disclosure provide a display panel and an electronic device, wherein the display panel comprises: a substrate, the substrate comprises a display area and a non-display area; the non-display area is located outside the display area, and a plurality of virtual sub-pixels are arranged on the non-display area; a plurality of display sub-pixels, a plurality of power supply voltage lines and a plurality of data signal lines are arranged on the display area, and the display sub-pixels comprise: a display pixel driving circuit, and a light-emitting unit driven to emit light by the display pixel driving circuit; the power supply voltage line and the data signal line are connected to the display pixel driving circuit; the display pixel driving circuit comprises at least a first transistor group and a second transistor connected to the first transistor group, and the first transistor group and the second transistor both comprise an active layer; the first transistor group comprises at least two first transistors connected in series, and the active layers of the two first transistors are connected via a channel connection region; and the data signal line is connected to the second transistor.

The invention discloses a display panel, a display device and a display terminal, and the display panel comprises an array substrate which comprises a light-emitting side and a backlight side which is oppositely arranged; the wiring layer is located on the backlight side of the array substrate, and the wiring layer comprises at least one signal line; the at least one pixel circuit is located on the side, away from the wiring layer, of the array substrate, and the signal line at least penetrates through part of the array substrate and is connected with the pixel circuit signal line. According to the array substrate, the wiring layer is arranged on the backlight side of the array substrate, the signal lines located on the wiring layer and the pixel circuit signal lines are arranged along the two sides of the array substrate respectively, direct coupling between the signal lines is avoided, and therefore coupling capacitance or mutual inductance is reduced. According to the technical scheme provided by the invention, the problem of non-uniform display caused by signal attenuation and signal delay during signal transmission of a large-size OLED display screen in related technologies is solved, the quality of a display picture is improved, and further, the application of an OLED display product in the field of large-size display is facilitated.

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a substrate and a shielding metal layer located on the substrate; the dummy metal layer is located on the substrate and located above the shielding metal layer; the grounding ring is located on the substrate and surrounds the pseudo metal layer, the grounding ring is provided with an opening, the grounding ring is electrically connected with the shielding metal layer, and the grounding ring is used for grounding; and the capacitor is positioned above the dummy metal layer and is positioned right above the shielding metal layer. The invention is beneficial to improving the quality factor of the semiconductor structure.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

The present application discloses a signal detection module and device, a display panel, and a display device, and relates to the field of fingerprint recognition technology. The control line and the output signal line in the signal detection module extend along a first direction, and the input signal line extends along a second direction. Therefore, the output signal line will not intersect with the control line, but only with the input signal line. In this way, the coupling capacitance generated by the output signal line and other signal lines can be reduced, and the noise of the recognition signal transmitted by the output signal line can be reduced, thereby improving the recognition effect.

The invention discloses a storage unit and a manufacturing method thereof, and a storage array, and the storage unit comprises a substrate which is provided with an active region, and the active region is internally provided with a groove; the first floating gate structure and the second floating gate structure are located in the groove; a barrier layer located on the surfaces of the first floating gate structure and the second floating gate structure; the common source layer is located in a first region of the active region, and the first drain layer and the second drain layer are located in a second region of the active region; the word line layer is located in the groove and covers the first floating gate structure and the second floating gate structure; and the bit line layer is electrically connected with the first drain layer and the second drain layer. The first floating gate structure and the second floating gate structure are located in the groove, and the first floating gate structure and the second floating gate structure cover part of the side wall and part of the bottom surface of the groove, so that a channel correspondingly formed by the first floating gate structure and the second floating gate structure is of a cambered surface structure, and the size of a channel region is increased; therefore, the coupling effect of the word line layer on the channel is enhanced, and the writing and erasing efficiency is improved.

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a data routing layer, an intermediate layer, and an anode layer. The data routing layer is disposed on the substrate and includes data signal lines. The intermediate layer is disposed on the data routing layer. The anode layer is disposed on the side of the intermediate layer away from the substrate and includes a shielding portion. The orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the data signal lines on the substrate. This array substrate can reduce the coupling capacitance between the data routing layer and the cathode, thereby improving horizontal crosstalk and enhancing the display effect.

This disclosure provides a semiconductor structure and its fabrication method. The structure includes: a plurality of active regions stacked in a vertical direction, the active regions extending in a first horizontal direction, and the plurality of active regions located on the same layer being spaced apart in a second horizontal direction, the first horizontal direction and the second horizontal direction intersecting; word lines covering a portion of the active regions and extending in the second horizontal direction; a plurality of bit lines spaced apart in the second horizontal direction, the bit lines extending in a vertical direction and connected to one end of the active regions; and an air gap structure including a first sub-section and a second sub-section, the first sub-section extending in a vertical direction and located at least between adjacent bit lines in the second horizontal direction, and the second sub-section located at least between adjacent word lines arranged in the vertical direction.

A display substrate and a display panel are disclosed. The display substrate includes a display area, a light-transmitting area, and a transition area. The transition area surrounds the light-transmitting area, and the display area surrounds the transition area. The display substrate includes a base, a first conductive layer, at least two intermediate conductive layers, and a second conductive layer, which are sequentially stacked on one side of the base. Multiple data lines are sequentially arranged along a first direction and extend from the display area to the transition area. In any two adjacent data lines in the transition area, one is located in the first conductive layer, and the other is located in the second conductive layer. This display substrate can improve or eliminate vertical bright bar mura defects appearing in parts of the display area corresponding to the light-transmitting area and the transition area, thereby improving the display effect of the display substrate.

This application provides a display panel and a display device aimed at improving antenna performance. The display panel includes: a support layer comprising a conductive material; and an antenna layer disposed on one side of the support layer in the thickness direction of the display panel, the antenna layer including an antenna element; wherein the support layer includes a through gap, and the projection of the antenna element in the thickness direction and the projection of the gap in the thickness direction at least partially overlap.

Embodiments of the present disclosure disclose a semiconductor device and a preparation method thereof, and an electronic device. The semiconductor device comprises: a substrate; a plurality of memory cell layers stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer comprising a plurality of memory cells arranged in an array; a memory cell comprising a transistor, the transistor comprising a gate electrode extending along a second direction parallel to a surface of the substrate and a semiconductor layer covering part of the gate electrode; a plurality of bit lines extending along the first direction, each bit line being connected to one of two side walls opposite to each other along a third direction parallel to the surface of the substrate of the semiconductor layer of a plurality of memory cells arranged along the first direction; a plurality of word lines extending along the third direction, each word line being connected to one of two end faces opposite to each other along the second direction of the gate electrode of a plurality of memory cells arranged along the third direction in the same memory cell layer; wherein the first direction is perpendicular to the second direction and the third direction, and the second direction intersects the third direction.

The embodiment of the invention provides a display substrate, a manufacturing method thereof and a display panel. The display substrate comprises a substrate body, a plurality of grid lines, a plurality of data lines, a plurality of grid leads and a plurality of data leads, wherein the grid lines, the data lines, the grid leads and the data leads are located on the surface of the substrate body. The substrate body is provided with a display area and a peripheral area. In the display area, a plurality of grid lines and data lines intersect to define a plurality of pixel areas. A plurality of grid leads and data leads which are located in the peripheral area and are in different layers are alternately arranged in the first direction, and the grid leads and the data lines are correspondingly and electrically connected with the grid lines and the data leads respectively. First leads exist in the gate leads and the data leads, each first lead comprises M first lead sections and M-1 second lead sections which are alternately arranged in the second direction, and a plurality of connecting sections, each first lead section is located between every two adjacent second leads, and each second lead section is located between every two adjacent second leads; and at least two second leads are spaced between the second lead section and the first lead section in the first direction. The display panel can improve poor display when the display panel is refreshed.

The invention provides a touch screen, electronic equipment, a protective shell and an equipment suite, the touch screen comprises a plurality of touch units, and the plurality of touch units are arranged in an array; each touch unit comprises an insulating layer, and a driving electrode and an induction electrode which are arranged on the insulating layer, and the driving electrode and the induction electrode are mutually insulated; wherein in the thickness direction of the touch unit, the orthographic projection area of the driving electrodes on the insulating layer is larger than the orthographic projection area of the sensing electrodes on the insulating layer, the touch screen can improve the screen shaking problem generated during multi-finger touch, and the touch effect and the use experience of the electronic equipment are improved.

The invention discloses a silicon through hole conductive structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a first dielectric structure on the surface of the substrate and a second dielectric structure on the surface of the first dielectric structure; forming a first opening in the second dielectric structure, wherein the first opening has a first projection on the surface of the substrate; a plurality of second openings are formed in the first medium structure and the substrate, the second openings are communicated with the first openings, each second opening has a second projection on the surface of the substrate, and the second projections are within the range of the first projection; and forming a first conductive plug structure in the first opening and each second opening. According to the forming method of the through-silicon-via conductive structure, the electric leakage possibility of the semiconductor structure is reduced, the coupling capacitance of the semiconductor structure is reduced, and the performance stability of the semiconductor structure is improved.