308results about How to "Reduce coupling capacitance" patented technology

A touch device includes a patterned sensing electrode structure, an insulating layer and a patterned common electrode layer. The patterned sensing electrode structure is disposed on a surface of a substrate, defining a plurality of displaying regions and a light-shielding region. The patterned sensing electrode structure corresponds to the light-shielding region, and exposes the displaying regions. The insulating layer covers the patterned sensing electrode structure. The patterned common electrode layer is disposed on the insulating layer, and the patterned common electrode layer includes a plurality of electrode portions corresponding to the displaying regions and a plurality of connecting portions disposed between the adjacent electrode portions and electrically connected to the electrode portions.

A liquid crystal display (“LCD”) capable of improving display quality includes a first insulating substrate, gate wiring lines formed on the first insulating substrate and extending in a first direction, data wiring lines insulated from and crossing the gate wiring lines and extending in a second direction, and pixel electrodes, each of which includes first and second sub-pixel electrodes that are applied with different data voltages from the data wiring lines, in which at least a part of the second sub-pixel electrode overlaps the data wiring lines.

The invention provides a shifting register unit, a gate driving circuit and a display device, and relates to the technical field of display. The coupling capacitance of a thin film transistor can be reduced. Noise of an output signal can be reduced. The shifting register unit comprises an input module, a control module, a restoration module, an upwards-pulling module, a downwards-pulling module and a noise reduction module. The shifting register unit, the gate driving circuit and the display device are used for achieving scanning driving.

The invention discloses a structure for a touch control device and a touch control display panel. The touch control device comprises a patterned sensing electrode structure, an insulating layer and a patterned sharing electrode layer. The patterned sensing electrode structure is arranged on the surface of a substrate defined with a plurality of display areas and a shading area, wherein the display areas are exposed corresponding to the shading area. The insulating layer covers the patterned sensing electrode structure. The patterned sharing electrode layer is arranged on the surface of the insulating layer, and comprises a plurality of electrode parts corresponding to the display areas and a plurality of connecting parts arranged between adjacent electrode parts and electrically connected to the electrode parts. The touch control device provides the patterned sensing electrode structure corresponding to the shade area, coordinately provides the electrode parts of the patterned sharing electrode layer corresponding to the display areas, and reduces area of the connecting parts to reduce superposition area of the patterned sensing electrode structure and the patterned sharing electrode layer, so as to reduce coupling capacitance thereof and promote intensity of sensed signals sensed by the patterned sensing electrode structure.

The invention provides an array substrate and a display panel. The array substrate comprises a non-display area and a display area, wherein the non-display area comprises a first non-display area anda second non-display area, the display area comprises a normal display area and a wire distribution area; the first non-display area surrounds the normal display area, the normal display area surrounds the wire distribution area, the wire distribution area surrounds the second non-display area, and the second non-display area comprises a perforation area. According to the technical scheme, data leads corresponding to subpixels which are simultaneously charged are arranged in an overlapping manner, so that the number of the data leads arranged in a same layer of the wire distribution area is reduced, the area of the wire distribution area is reduced, and a narrow frame design between the second non-display area and the normal display area is realized. Moreover, since the number of the dataleads in the same layer of the wire distribution area is reduced, a linear distance between the adjacent data leads is increased, so that the coupling capacitance between the adjacent data leads arranged on the same layer is reduced.

The invention discloses a display panel, a method for preparing the same and a display device. The display panel comprises at least one first data line. The first data lines penetrate a functional device zone. The display panel, the method and the display device have the advantages that the portions, which penetrate the functional device zone, of the first data lines are first transparent electricconduction lines, arrangement regions for data lines which penetrate a second non-display zone can be increased, accordingly, the distances between the data lines which penetrate the second non-display zone can be increased, coupling resistance between the adjacent data lines can be lowered, and the problem of abnormal display of existing display panels due to the fact existing data lines are excessively densely arranged can be solved; the display panel is provided with the first transparent electric conduction lines, the quantities of data lines required to be arranged in a border zone can be reduced, accordingly, the purpose of reducing the areas occupied by the border zone can be achieved, and the screen-to-body ratio of the display panel further can be increased.

A capacitive touch panel and a display device using the capacitive touch panel are provided. The capacitive touch panel includes a plurality of first direction electrode strings and second direction electrode strings. Each first direction electrode string has a plurality of first electrodes while each second direction electrode has a plurality of second electrodes. In order to reduce the lateral capacitance between adjacent electrodes, width of the first electrode is reduced from the middle to two sides of the electrode along a second direction. In addition, the first electrode has a perimeter surrounding itself. Each quarter of the perimeter of the first electrode facing the adjacent second electrode has a first slope change rate and a different second slope change rate.

A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.

A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.

A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

A flash EEPROM array includes a first row of EEPROM cells having a first floating gate electrode therein and a second row of EEPROM cells having a second floating gate electrode therein. The first floating gate electrode includes at least one horizontal segment and at least one vertical segment, which collectively define a first L-shaped portion of the first floating gate electrode that faces a first direction. The second floating gate electrode includes at least one horizontal segment and at least one vertical segment that collectively define a second L-shaped portion of the second floating gate electrode that faces a second direction opposite the first direction.

The invention provides an array substrate, a liquid crystal display panel and a display device. The array substrate comprises a substrate, a plurality of scanning lines, a plurality of thin film transistors arranged in a matrix form, a flattening layer, a filling electrode and a pixel electrode, wherein the scanning lines and multiple pieces of data are arranged in a cross manner; each thin film transistor comprises a gate, an active layer and a drain electrode; the flattening layer covers the gate, the active layer and the drain electrode; a through hole penetrating through the flattening layer is formed in a position, which corresponds to the drain electrode, of the flattening layer; the drain electrode is positioned inside the through hole; the filling electrode is positioned in the through hole, is connected with the drain electrode and covers the drain electrode; the pixel electrode is indirectly connected to the drain electrode through the filling electrode. According to the array substrate disclosed by the invention, the distance between the data line and the pixel electrode is enlarged, the influence of the data line on the pixel electrode is reduced, and a crosstalk phenomenon of the display device is improved; a segment gap of the drain electrode is compensated through the filling electrode, the line breakage problem of the pixel electrode is improved, and the yield of the display device is improved.

A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In the case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.

A display apparatus includes: a first gate line extending in a second direction crossing a first direction; a row line extending in the first direction and electrically connected to the first gate line; a first data line spaced from the first gate line along the first direction and extending in the second direction; a second data line adjacent to the first data line and extending in the second direction; a first sub-pixel electrically connected to the first data line; and a second sub-pixel electrically connected to the second data line.

The invention discloses a split gate type flash memory which comprises a semiconductor substrate, a word line, two discrete storage bit units and oxidation layers, wherein the word line is located at the bottom surface of the semiconductor substrate; the two storage bit units are located at two sides of the word line; the oxidation layers are arranged between the two storage bit units and the word line; each storage bit unit comprises a first insulation layer which is located on the bottom surface of the semiconductor substrate, a floating gate which is located on the surface of the first insulation layer, a second insulation layer which is located on the surface of the floating gate, a control gate which is located on the surface of the second insulation layer and a side wall structure which covers the floating gate and the control gate; each floating gate comprises a first floating gate and a second floating gate; and the distance between each first floating gate and the word line is greater than the distance between each second floating gate and the word line. The distance between the first floating gates and the word line is greater than the distance in the prior art, so that the coupling capacitance between the floating gates and the word line is smaller than the capacitance in the prior art, the coupling capacitance between the word line and the floating gates is as small as possible and then the erasing efficiency and the read-write efficiency of the flash memory are improved.

A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit.

Standard unit general routing method of coupling effect in time delay optimization characterizes in making up time delay optimization routing tree under the condition that any of the wire nets is not restrained to further optimize outing congestion to estimated the link electricity parameter with successively connected linking load model based on empiric analog after elimianting congestion edge, to compute the link delay with congruence variation technology to compute gate delay etc. three steps to calculate the path general delay value with looking-up table+interpolation based on the delay information table given by user, then enhancing to considerate the key path up wire net weighted value of the couple effect to reduce routing density adjacent to the wire net, so as to reduce couple condenser and general path delay to optimize the circuit time delay.

A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.