8results about How to "Reduce coupling capacitance" patented technology

The invention discloses a display panel, a display device and a display terminal, and the display panel comprises an array substrate which comprises a light-emitting side and a backlight side which is oppositely arranged; the wiring layer is located on the backlight side of the array substrate, and the wiring layer comprises at least one signal line; the at least one pixel circuit is located on the side, away from the wiring layer, of the array substrate, and the signal line at least penetrates through part of the array substrate and is connected with the pixel circuit signal line. According to the array substrate, the wiring layer is arranged on the backlight side of the array substrate, the signal lines located on the wiring layer and the pixel circuit signal lines are arranged along the two sides of the array substrate respectively, direct coupling between the signal lines is avoided, and therefore coupling capacitance or mutual inductance is reduced. According to the technical scheme provided by the invention, the problem of non-uniform display caused by signal attenuation and signal delay during signal transmission of a large-size OLED display screen in related technologies is solved, the quality of a display picture is improved, and further, the application of an OLED display product in the field of large-size display is facilitated.

The invention belongs to the technical field of electronic circuit design, and discloses a differential signal Fanout structure for improving the integrity of a high-speed signal, and the structure comprises a PCB substrate; the differential signal pair is arranged on the PCB substrate, the differential signal pair comprises a P signal wire and an N signal wire, and the P signal wire and the N signal wire are respectively used for connecting chip pins; and a ground shield unit. By adopting layered fan-out and large-spacing decoupling design, crosstalk of high-speed differential signals is remarkably reduced, the limitation that tight coupling wiring must be conducted on the same layer in a traditional Fanout structure is broken through, P signals and N signals are arranged on the surface layer and the inner layer of a PCB respectively, and therefore the signal transmission efficiency is improved. By means of isolation of a vertical space, maximization of horizontal projection spacing is achieved (a decoupling spacing area is formed), inter-line coupling capacitance is remarkably reduced, far-end crosstalk is remarkably reduced through the structure, and the signal-to-noise ratio and eye pattern opening of a high-speed link are improved.

The invention discloses a storage unit and a manufacturing method thereof, and a storage array, and the storage unit comprises a substrate which is provided with an active region, and the active region is internally provided with a groove; the first floating gate structure and the second floating gate structure are located in the groove; a barrier layer located on the surfaces of the first floating gate structure and the second floating gate structure; the common source layer is located in a first region of the active region, and the first drain layer and the second drain layer are located in a second region of the active region; the word line layer is located in the groove and covers the first floating gate structure and the second floating gate structure; and the bit line layer is electrically connected with the first drain layer and the second drain layer. The first floating gate structure and the second floating gate structure are located in the groove, and the first floating gate structure and the second floating gate structure cover part of the side wall and part of the bottom surface of the groove, so that a channel correspondingly formed by the first floating gate structure and the second floating gate structure is of a cambered surface structure, and the size of a channel region is increased; therefore, the coupling effect of the word line layer on the channel is enhanced, and the writing and erasing efficiency is improved.

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a data routing layer, an intermediate layer, and an anode layer. The data routing layer is disposed on the substrate and includes data signal lines. The intermediate layer is disposed on the data routing layer. The anode layer is disposed on the side of the intermediate layer away from the substrate and includes a shielding portion. The orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the data signal lines on the substrate. This array substrate can reduce the coupling capacitance between the data routing layer and the cathode, thereby improving horizontal crosstalk and enhancing the display effect.

This disclosure provides a semiconductor structure and its fabrication method. The structure includes: a plurality of active regions stacked in a vertical direction, the active regions extending in a first horizontal direction, and the plurality of active regions located on the same layer being spaced apart in a second horizontal direction, the first horizontal direction and the second horizontal direction intersecting; word lines covering a portion of the active regions and extending in the second horizontal direction; a plurality of bit lines spaced apart in the second horizontal direction, the bit lines extending in a vertical direction and connected to one end of the active regions; and an air gap structure including a first sub-section and a second sub-section, the first sub-section extending in a vertical direction and located at least between adjacent bit lines in the second horizontal direction, and the second sub-section located at least between adjacent word lines arranged in the vertical direction.

A display substrate and a display panel are disclosed. The display substrate includes a display area, a light-transmitting area, and a transition area. The transition area surrounds the light-transmitting area, and the display area surrounds the transition area. The display substrate includes a base, a first conductive layer, at least two intermediate conductive layers, and a second conductive layer, which are sequentially stacked on one side of the base. Multiple data lines are sequentially arranged along a first direction and extend from the display area to the transition area. In any two adjacent data lines in the transition area, one is located in the first conductive layer, and the other is located in the second conductive layer. This display substrate can improve or eliminate vertical bright bar mura defects appearing in parts of the display area corresponding to the light-transmitting area and the transition area, thereby improving the display effect of the display substrate.

This application provides a display panel and a display device aimed at improving antenna performance. The display panel includes: a support layer comprising a conductive material; and an antenna layer disposed on one side of the support layer in the thickness direction of the display panel, the antenna layer including an antenna element; wherein the support layer includes a through gap, and the projection of the antenna element in the thickness direction and the projection of the gap in the thickness direction at least partially overlap.

Embodiments of the present disclosure disclose a semiconductor device and a preparation method thereof, and an electronic device. The semiconductor device comprises: a substrate; a plurality of memory cell layers stacked at intervals along a first direction perpendicular to the substrate, each memory cell layer comprising a plurality of memory cells arranged in an array; a memory cell comprising a transistor, the transistor comprising a gate electrode extending along a second direction parallel to a surface of the substrate and a semiconductor layer covering part of the gate electrode; a plurality of bit lines extending along the first direction, each bit line being connected to one of two side walls opposite to each other along a third direction parallel to the surface of the substrate of the semiconductor layer of a plurality of memory cells arranged along the first direction; a plurality of word lines extending along the third direction, each word line being connected to one of two end faces opposite to each other along the second direction of the gate electrode of a plurality of memory cells arranged along the third direction in the same memory cell layer; wherein the first direction is perpendicular to the second direction and the third direction, and the second direction intersects the third direction.