Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; a plurality of first isolation grooves and a plurality of second isolation grooves are formed in the substrate, the first isolation grooves extend in the first direction, the second isolation grooves extend in the second direction, and the first direction and the second direction are parallel to the substrate and intersect with each other; the plurality of first isolation grooves and the plurality of second isolation grooves jointly isolate a plurality of active columns arranged in an array. The plurality of active columns are arranged in a row along a first direction; a plurality of bit lines arranged at intervals; the bit lines are located below the active columns and extend in the first direction, and the active columns located in the same row are sequentially connected in series; a plurality of air gap structures; the air gap structures are located between the adjacent bit lines and located at the bottoms of the corresponding first isolation grooves. The semiconductor structure can improve the read-write speed of the memory, so that the memory has more excellent electrical performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of dynamic random access memory (DRAM) technology, the size of storage cells is getting smaller and smaller, and its array architecture is from 8F to 2 Go to 6F 2 Then to 4F 2 (F: minimum pattern size obtainable under given process conditions).

[0003] However, as the size of memory cells continues to decrease, the spacing between adjacent bit lines in the memory also continues to decrease, thereby increasing the coupling capacitance between the bit lines, which has an adverse effect on the read and write speed and sense margin of the memory. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, in order to address the deficiencies in the prior art.

[0005] In one aspect, the present application provides a semiconductor structure, comprising:

[0006] A substrate; the substrate has a plurality of first isolation grooves and a plurality of second isolation grooves, the first isolation grooves extend along a first direction, the second isolation grooves extend along a second direction, the first direction and the second direction are parallel to the substrate and intersect each other; the plurality of first isolation grooves and the plurality of second isolation grooves together isolate a plurality of active pillars arranged in an array; the plurality of active pillars are arranged in a row along the first direction;

[0007] A plurality of bit lines arranged at intervals; the bit lines are located below the active pillars and extend along the first direction to sequentially connect the active pillars in the same row in series;

[0008] A plurality of air gap structures; the air gap structures are located between adjacent bit lines and at the bottom of the corresponding first isolation trench.

[0009] In some embodiments, the air gap structure comprises:

[0010] An isolation film covers the sidewalls of the adjacent bit lines and forms a closed space;

[0011] and an isolation air gap located within the enclosed space.

[0012] In some embodiments, a size of the air gap structure in a direction perpendicular to the substrate is greater than or equal to a size of the bit line in a direction perpendicular to the substrate.

[0013] In some embodiments, the substrate comprises: a first base, an isolation layer, and a second base stacked in layers; wherein:

[0014] The active pillar, the bit line and the air gap structure are all located in the first substrate, and the bit line and the air gap structure are also located on a surface of the isolation layer away from the second substrate, and the active pillar is also located on a surface of the bit line away from the isolation layer.

[0015] In some embodiments, the first substrate includes: a growth substrate and an epitaxial layer epitaxially grown on the surface of the growth substrate; wherein,

[0016] The bit line and the air gap structure are located on a surface of the growth substrate away from the epitaxial layer;

[0017] The active pillar includes a first portion isolated by the first isolation trench and the second isolation trench in the growth substrate, and a second portion isolated by the first isolation trench and the second isolation trench in the epitaxial layer.

[0018] In some embodiments, the isolation layer and the isolation film in the air gap structure are an integrated structure.

[0019] On the other hand, the present application also provides a method for preparing a semiconductor structure, comprising:

[0020] A substrate is provided; a plurality of bit lines extending along a first direction and arranged at intervals in a second direction are formed in the substrate, the first direction and the second direction are parallel to the substrate and intersect; an air gap structure is formed between the bit lines adjacent to each other in the second direction;

[0021] The substrate is etched to form a plurality of first isolation grooves and a plurality of second isolation grooves; the first isolation grooves extend along the first direction and are located above the corresponding air gap structure; the second isolation grooves extend along the second direction; the plurality of first isolation grooves and the plurality of second isolation grooves together isolate a plurality of active pillars arranged in an array; the plurality of active pillars are arranged in rows along the first direction, and the bit lines connect the active pillars in the same row in series in sequence.

[0022] In some embodiments, providing a substrate comprises:

[0023] Providing a growth substrate;

[0024] forming a bit line material layer on a surface of one side of the growth substrate;

[0025] forming a plurality of bit line isolation grooves penetrating the bit line material layer and extending into the growth substrate; the bit line isolation grooves extending along the first direction, the plurality of bit line isolation grooves separating the bit line material layer into a plurality of bit lines;

[0026] An isolation film with a closed space is formed on the groove wall and the groove opening of the bit line isolation groove, and an isolation air gap is formed in the closed space; the air gap structure includes the isolation film and the isolation air gap.

[0027] In some embodiments, forming a bit line material layer on a side surface of the growth substrate includes:

[0028] forming an initial bit line material layer on a surface of one side of the growth substrate;

[0029] The initial bit line material layer is subjected to metal silicidation treatment by adopting a rapid thermal annealing process to form the bit line material layer.

[0030] In some embodiments, the isolation film having the closed space is formed on the groove wall and the groove opening of the bit line isolation groove by chemical vapor deposition process; the deposition rate of the isolation film is greater than 7 nm / min.

[0031] In some embodiments, providing a substrate further comprises:

[0032] forming an isolation layer covering the bit line and the isolation film on a side of the bit line and the isolation film away from the growth substrate;

[0033] flipping the structure obtained after forming the isolation layer, and attaching the isolation layer to a second substrate;

[0034] The etching of the substrate to form a plurality of first isolation grooves and a plurality of second isolation grooves is performed after the isolation layer is attached to the second base.

[0035] In some embodiments, the isolation layer and the isolation film are formed by the same deposition process.

[0036] In some embodiments, providing a substrate further comprises:

[0037] An epitaxial layer is formed on a surface of the growth substrate away from the isolation layer; the growth substrate and the epitaxial layer together constitute a first substrate; the substrate includes the first substrate, the isolation layer and the second substrate;

[0038] The etching of the substrate to form a plurality of first isolation trenches and a plurality of second isolation trenches comprises:

[0039] The epitaxial layer and the growth substrate are etched to form the first isolation trench and the second isolation trench; the air gap structure is located at the bottom of the first isolation trench; the active column includes: a first part isolated by the first isolation trench and the second isolation trench in the growth substrate, and a second part isolated by the first isolation trench and the second isolation trench in the epitaxial layer.

[0040] In some embodiments, after forming a plurality of the first isolation trenches and a plurality of the second isolation trenches, the method for preparing the semiconductor structure further includes:

[0041] forming a gate dielectric layer that conformally covers at least the sidewalls of the channel region of the active pillar;

[0042] A gate is formed to cover the channel region of the active pillar.

[0043] In some embodiments, the forming of a gate dielectric layer that conformally covers at least the sidewalls of the channel region of the active pillar comprises:

[0044] forming a first gate dielectric material layer; the first gate dielectric material layer is filled in the first isolation trench and covers the top surface of the active column and the sidewall of the active column in the first direction;

[0045] forming a first isolation dielectric material layer; the first isolation dielectric material layer is filled in the second isolation groove and covers the top surface of the first gate dielectric material layer;

[0046] Removing a portion of the first gate dielectric material layer so that the top surface of the retained first gate dielectric material layer is not higher than the top surface of the active pillar; the retained first gate dielectric material layer is used as the second gate dielectric material layer; and removing a portion of the first isolation dielectric material layer so that the top surface of the retained first isolation dielectric material layer is not higher than the top surface of the active pillar; the retained first isolation dielectric material layer is used as the first isolation dielectric layer;

[0047] Removing a portion of the height of the second gate dielectric material layer to expose the top of the active pillar; the remaining second gate dielectric material layer is used as a third gate dielectric material layer;

[0048] Forming a sidewall mask layer; the sidewall mask layer covers the sidewall of the exposed top of the active column;

[0049] Based on the sidewall mask layer, a portion of the third gate dielectric material layer formed on the sidewall of the active pillar in the first direction is removed to expose the channel region of the active pillar in the first direction; and the third gate dielectric material layer formed on the sidewall of the active pillar in the second direction is removed;

[0050] The active pillar is etched to form a receiving groove on two opposite sides of the channel region in the first direction; and the inner wall of the receiving groove is conformally covered with the fourth gate dielectric material layer; the third gate dielectric material layer and the fourth gate dielectric material layer together constitute the gate dielectric layer.

[0051] The semiconductor structure and the method for preparing the same provided by the present application have at least the following beneficial effects:

[0052] In the embodiment of the present application, an air gap structure is provided between adjacent bit lines. Since the air gap structure has a lower dielectric constant, the air gap structure provided between adjacent bit lines can effectively reduce the coupling capacitance between adjacent bit lines in the semiconductor structure, reduce the mutual influence of charges between adjacent bit lines and cause signal interference in the memory read and write operations, thereby improving the sensing margin of the memory and making the memory have higher reliability. The lower coupling capacitance between adjacent bit lines is also conducive to increasing the speed of change of the bit line voltage, making the signal transmission speed higher, thereby improving the read and write speed of the memory, and making the memory have better electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a schematic top view in the aa' direction and the cc' direction in the embodiment of the present application;

[0055] Figure 2 Figure (a) is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present application in the aa' direction; Figure 2 Figure (b) is Figure 2 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0056] Figure 3 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;

[0057] Figure 4 A schematic flow chart of step S100 in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0058] Figure 5 A schematic flow chart of step S100 in a method for preparing a semiconductor structure provided in some other embodiments of the present application;

[0059] Figure 6 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after providing a growth substrate in the method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 6 Figure (b) is Figure 6 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0060] Figure 7 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming an initial bit line material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 7 Figure (b) is Figure 7 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0061] Figure 8 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after a bit line material layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 8 Figure (b) is Figure 8 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0062] Fig. 9 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after a bit line isolation trench is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig. 9 Figure (b) is Fig. 9 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0063] Fig.10 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming an isolation layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.10 Figure (b) is Fig.10 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0064] Fig.11 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after the isolation layer is formed inverted in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.11 Figure (b) is Fig.11 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0065] Fig.12Figure (a) is a schematic diagram of the cross-sectional structure of a structure obtained after forming an epitaxial layer in the semiconductor structure preparation method provided in some embodiments of the present application in the aa' direction; Fig.12 Figure (b) is Fig.12 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0066] Fig.13 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after sequentially depositing a first silicon oxide layer, a polysilicon layer, a first silicon oxynitride layer, a spin-coated hard mask layer and a second silicon oxynitride layer on a surface of one side of a substrate in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.13 Figure (b) is Fig.13 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0067] Fig.14 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a first isolation trench in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.14 Figure (b) is Fig.14 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0068] Fig.15 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a second isolation trench in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.15 Figure (b) is Fig.15 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0069] Fig.16 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a first gate dielectric material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.16 Figure (b) is Fig.16 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0070] Fig.17 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a first isolation dielectric material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.17 Figure (b) is Fig.17 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0071] Fig.18FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a second gate dielectric material layer and a first isolation dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.18 Figure (b) is Fig.18 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0072] Fig.19 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a third gate dielectric material layer in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.19 Figure (b) is Fig.19 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0073] Fig. 20 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after forming a sidewall mask layer in the method for preparing a semiconductor structure provided in some embodiments of the present application; Fig. 20 Figure (b) is Fig. 20 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0074] Fig.21 FIG. (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after exposing a channel region of an active pillar in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.21 Figure (b) is Fig.21 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0075] Fig. 22 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after a gate dielectric layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig. 22 Figure (b) is Fig. 22 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0076] Fig.23 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after a gate is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.23 Figure (b) is Fig.23 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0077] Fig.24 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after a filling dielectric layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application; Fig.24 Figure (b) is Fig.24 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction;

[0078] Fig.25 Figure (a) is a schematic diagram of the cross-sectional structure of the structure obtained after forming a protective layer in the preparation method of the semiconductor structure provided in some embodiments of the present application in the aa' direction, Fig.25 Figure (a) is also a schematic diagram of a cross-sectional structure of a semiconductor structure in the aa' direction provided by some other embodiments of the present application; Fig.25 Figure (b) is Fig.25 (a) is a schematic diagram of the cross-sectional structure of the structure in the cc' direction. Fig.25 FIG. (b) is also a schematic diagram of the cross-sectional structure of the semiconductor structure in the cc' direction provided in some other embodiments of the present application.

[0079] Description of reference numerals:

[0080] 1. substrate; 10. active pillar; 10A. channel region; 10B. connection end; 101. first part; 102. second part; 11. first base; 111. growth base; 112. epitaxial layer; 12. isolation layer; 13. second base; 2. bit line; 20', initial bit line material layer; 2', bit line material layer; 2A, first silicon oxide layer; 2B, polysilicon layer; 2C, first silicon oxynitride layer; 2D, spin-on hard mask layer; 2E, second oxynitride layer Silicon layer; 3. air gap structure; 31. isolation film; 32. isolation air gap; 4. gate dielectric layer; 41. first gate dielectric material layer; 42. second gate dielectric material layer; 43. third gate dielectric material layer; 44. fourth gate dielectric material layer; 5. gate; 6. first isolation dielectric layer; 6', first isolation dielectric material layer; 7. sidewall mask layer; 8. filling dielectric layer; 9. protective layer; T11. first isolation trench; T12. second isolation trench; T21. bit line isolation trench. DETAILED DESCRIPTION

[0081] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0083] It should be understood that when an element or layer is referred to as being "on" or "adjacent to...", it may be directly on or adjacent to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first isolation trench may be referred to as a second isolation trench, and similarly, a second isolation trench may be referred to as a first isolation trench; the first isolation trench and the second isolation trench are different isolation trenches.

[0084] Spatially relative terms such as "below," "above," etc., may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "below" will be oriented as "above" the other elements or features. Therefore, the exemplary terms "below" and "above" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0085] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0086] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0087] As the size of memory cells continues to decrease, the spacing between adjacent bit lines in the memory also continues to decrease, thereby increasing the coupling capacitance between the bit lines, which has an adverse effect on the read and write speed and sense margin of the memory.

[0088] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, the details of which will be described in the subsequent embodiments.

[0089] In one aspect, the present application provides a semiconductor structure according to some embodiments.

[0090] As an example, the semiconductor structure can be used to form a semiconductor device (such as DRAM), and the DRAM can include a transistor structure and a capacitor structure connected to the transistor structure, the capacitor structure is used to store data, and the transistor structure is used to read data in the capacitor structure or write data into the capacitor structure. It can be understood that the semiconductor structure provided in the embodiment of the present application can be used as a component of the transistor structure in the DRAM, for example, it can be a vertical channel array transistor (Vertical channel transistor, referred to as VCT), but it is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0091] It should be noted that, in the embodiment of the present application, the first direction and the second direction are parallel to the substrate and intersect. Figure 1 The aa' direction and the cc' direction in the present application are shown. The following takes the first direction as the aa' direction and the second direction as the cc' direction as an example to illustrate the embodiment of the present application.

[0092] See also Figure 2 Figure (a) and Figure 2 As shown in FIG. 2( b ), in some embodiments, the semiconductor structure includes a substrate 1 , a plurality of bit lines 2 arranged at intervals, and a plurality of air gap structures 3 .

[0093] The substrate 1 has a plurality of first isolation trenches T11 and a plurality of second isolation trenches T12. The first isolation trenches T11 extend along a first direction (e.g., aa' direction), and the second isolation trenches T12 extend along a second direction (e.g., cc' direction). The plurality of first isolation trenches T11 and the plurality of second isolation trenches T12 can together isolate a plurality of active pillars 10 arranged in an array.

[0094] It can be understood that the plurality of active pillars 10 are arranged in a row along the first direction (eg, the aa′ direction).

[0095] The bit lines 2 are located below the active pillars 10 and extend along a first direction (eg, the aa′ direction) to sequentially connect the active pillars 10 in the same row.

[0096] The air gap structure 3 is located between adjacent bit lines 2 and at the bottom of the corresponding first isolation trench T11 .

[0097] In the semiconductor structure provided in the above embodiment, an air gap structure 3 is provided between adjacent bit lines 2. Since the air gap structure 3 has a lower dielectric constant, the provision of the air gap structure 3 between adjacent bit lines 2 can effectively reduce the coupling capacitance between adjacent bit lines 2 in the semiconductor structure, and reduce the mutual influence of charges between adjacent bit lines 2 to cause signal interference in the memory read and write operations. Therefore, in the process of preparing the memory, the preparation method of the above semiconductor structure can be used to improve the sensing margin of the memory, so that the memory has higher reliability. The lower coupling capacitance between adjacent bit lines 2 is also conducive to improving the speed of change of the bit line 2 voltage, so that the signal transmission speed is higher. Therefore, the preparation method of the above semiconductor structure can also improve the read and write speed of the memory, so that the memory has better electrical performance.

[0098] The embodiment of the present application does not specifically limit the size of the air gap structure 3 in the direction perpendicular to the substrate 1. As an example, the size of the air gap structure 3 in the direction perpendicular to the substrate 1 is greater than or equal to the size of the bit line 2 in the direction perpendicular to the substrate 1.

[0099] In the above example, the size of the air gap structure 3 in the direction perpendicular to the substrate 1 is greater than or equal to the size of the bit line 2 in the direction perpendicular to the substrate 1, that is, the positive projection of the air gap structure 3 in the direction perpendicular to the substrate 1 can cover the bit line 2, which is beneficial to further reduce the coupling capacitance between adjacent bit lines 2 in the semiconductor structure, and avoid the mutual influence of charges between adjacent bit lines 2 to cause signal interference in memory reading and writing operations.

[0100] Please continue reading Figure 2 Figure (a) and Figure 2 As shown in FIG. 5( b ), in some embodiments, the air gap structure 3 may specifically include an isolation film 31 and an isolation air gap 32 .

[0101] The isolation film 31 covers the sidewalls of the adjacent bit lines 2 and forms a closed space; the isolation air gap 32 is located in the closed space.

[0102] Please continue reading Figure 2 Figure (a) and Figure 2 As shown in FIG. 5( b ), in some embodiments, the substrate 1 may specifically include a first base 11 , an isolation layer 12 , and a second base 13 which are stacked.

[0103] In the semiconductor structure provided in the above embodiment, the active pillar 10, the bit line 2 and the air gap structure 3 are all located in the first substrate 11, and the bit line 2 and the air gap structure 3 are also located on the surface of the isolation layer 12 away from the second substrate 13, and the active pillar 10 is also located on the surface of the bit line 2 away from the isolation layer 12.

[0104] Please continue reading Figure 2 Figure (a) and Figure 2 As shown in FIG. 5( b ), in some embodiments, the first substrate 11 may specifically include a growth substrate 111 and an epitaxial layer 112 epitaxially grown on a surface of the growth substrate 111 .

[0105] In the semiconductor structure provided by the above embodiment, the bit line 2 and the air gap structure 3 are located on the surface of the growth substrate 111 away from the epitaxial layer 112 .

[0106] As an example, the active pillar 10 may include a first portion 101 isolated in the growth substrate 111 by the first isolation trench T11 and the second isolation trench T12 , and a second portion 102 isolated in the epitaxial layer 112 by the first isolation trench T11 and the second isolation trench T12 .

[0107] In some embodiments, the isolation layer 12 and the isolation film 31 in the air gap structure 3 may be an integral structure.

[0108] It is understood that the semiconductor structure provided in the embodiment of the present application may also include some other technical features; for example, an isolation dielectric layer and a word line, etc., but not limited thereto. The specific location and preparation process of other technical features can be found in the subsequent embodiments.

[0109] On the other hand, the present application also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided in the aforementioned embodiment.

[0110] See also Figure 3 In some embodiments, the method for preparing the semiconductor structure may include the following steps:

[0111] S100: providing a substrate; forming a plurality of bit lines extending along a first direction and arranged at intervals in a second direction in the substrate, the first direction and the second direction are parallel to and intersect the substrate; forming an air gap structure between adjacent bit lines in the second direction.

[0112] S200: etching the substrate to form a plurality of first isolation grooves and a plurality of second isolation grooves; the first isolation grooves extend along a first direction and are located above the corresponding air gap structure; the second isolation grooves extend along a second direction; the plurality of first isolation grooves and the plurality of second isolation grooves together isolate a plurality of active pillars arranged in an array; the plurality of active pillars are arranged in rows along the first direction, and the bit lines connect the active pillars in the same row in series in sequence.

[0113] In the method for preparing the semiconductor structure provided in the above embodiment, an air gap structure is formed between adjacent bit lines. Since the air gap structure has a lower dielectric constant, the formation of the air gap structure between adjacent bit lines can effectively reduce the coupling capacitance between adjacent bit lines in the semiconductor structure, and reduce the mutual influence of charges between adjacent bit lines to cause signal interference in the memory read and write operations. Therefore, in the process of preparing the memory, the preparation method of the above semiconductor structure can be used to improve the sensing margin of the memory, so that the memory has higher reliability. The lower coupling capacitance between adjacent bit lines is also conducive to improving the speed of change of the bit line voltage, so that the signal transmission speed is higher. Therefore, the preparation method of the above semiconductor structure can also improve the read and write speed of the memory, so that the memory has better electrical performance.

[0114] See also Figure 4 In some embodiments, step S100 of providing a substrate may specifically include the following steps:

[0115] S110: providing a growth substrate.

[0116] S120: forming a bit line material layer on a surface of one side of the growth substrate.

[0117] S130: forming a plurality of bit line isolation trenches penetrating the bit line material layer and extending into the growth substrate; a first isolation trench extends along a first direction, and the plurality of bit line isolation trenches separate the bit line material layer into a plurality of bit lines.

[0118] S140: forming an isolation film having a closed space on the groove wall and the groove opening of the bit line isolation groove, wherein an isolation air gap is formed in the closed space; the air gap structure includes the isolation film and the isolation air gap.

[0119] See also Figure 5 In some embodiments, step S100 provides a substrate and may further include the following steps:

[0120] S150: forming an isolation layer covering the bit line and the isolation film on a side of the bit line and the isolation film away from the growth substrate.

[0121] S160: Turning over the structure after forming the isolation layer, and attaching the isolation layer to the second substrate.

[0122] It should be noted that, in the above embodiment, step S200 of etching the substrate to form a plurality of first isolation trenches and a plurality of second isolation trenches may be performed after step S160 of laminating the isolation layer to the second substrate.

[0123] It should be understood that although Figures 3 to 5The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 3 to 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0124] In order to more clearly illustrate the method for preparing the semiconductor structure provided in some embodiments of the present application, the following is combined with Figures 6 to 25 Understand some embodiments of the present application.

[0125] See also Figures 6 to 13 In step S100, a substrate 1 is provided. A plurality of bit lines 2 extending along a first direction and arranged at intervals in a second direction are formed in the substrate 1.

[0126] Specifically, an air gap structure 3 is formed between adjacent bit lines 2 in the second direction (eg, cc′ direction). The size of the air gap structure 3 in the direction perpendicular to the substrate 1 is greater than or equal to the size of the bit line 2 in the direction perpendicular to the substrate 1 .

[0127] In some embodiments, step S100 provides a substrate 1 , which may be specifically performed as follows steps S110 to S140 .

[0128] In step S110, Figure 6 Figure (a) and Figure 6 As shown in FIG. 8( b ), a growth substrate 111 is provided.

[0129] In step S120, Figures 7 and 8 As shown, a bit line material layer 2 ′ is formed on one side surface of the growth substrate 111 .

[0130] In step S130, Fig. 9 Figure (a) and Fig. 9 As shown in FIG. 1( b ), a plurality of bit line isolation trenches T21 are formed that penetrate the bit line material layer 2 ′ and extend into the growth substrate 111 . The bit line isolation trenches T21 extend along a first direction (eg, aa′ direction), and the plurality of bit line isolation trenches T21 separate the bit line material layer 2 ′ into a plurality of bit lines 2 .

[0131] In step S140, if Fig.10 Figure (a) and Fig.10As shown in FIG. 2( b ), an isolation film 31 having a closed space is formed on the groove wall and the groove opening of the bit line isolation groove T21 , and an isolation air gap 32 is formed in the closed space. The isolation film 31 and the isolation air gap 32 together constitute an air gap structure 3 .

[0132] For step S110, the embodiment of the present application does not specifically limit the constituent materials of the growth substrate 111. As an example, the growth substrate 111 can be composed of semiconductor materials, insulating materials, conductor materials or any combination of their material types. The growth substrate 111 can be a single-layer structure or a multi-layer structure. For example, the growth substrate 111 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (Ga As) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the growth substrate 111 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator, etc.

[0133] For step S120, as an example, the bit line material layer 2' may be formed by the following steps, for example:

[0134] like Figure 7 Figure (a) and Figure 7 As shown in FIG. 2( b ), an initial bit line material layer 20 ′ is formed on one side of the growth substrate 111 ; the initial bit line material layer 20 ′ may be made of materials such as titanium (Ti), cobalt (Co), nickel platinum alloy (NiPt), etc. Figure 8 Figure (a) and Figure 8 As shown in FIG. (b), the initial bit line material layer 20' is subjected to metal silicide treatment by using a rapid thermal annealing (RTA) process or other heating process to form a bit line material layer 2'. Correspondingly, the bit line material layer 2' can be, for example, titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi2), etc.

[0135] In the method for preparing the semiconductor structure provided in the above example, due to the rapid heating and cooling characteristics of the RTA process, better uniformity can be achieved, so that the metal silicidation reaction occurs evenly on the surface of the entire growth substrate 111, thereby improving the structural uniformity of the resulting bit line material layer 2', which is beneficial to improving the production yield of the preparation method.

[0136] For step S140, the embodiment of the present application does not specifically limit the method for forming the isolation film 31. As an example, the isolation film 31 with a closed space can be formed on the groove wall and groove opening of the bit line isolation groove T21 by using, but not limited to, a chemical vapor deposition (CVD) process. In an actual embodiment, the deposition conditions during the CVD process can be controlled, and the parameters of the CVD process, such as temperature, pressure and / or gas flow, can be adjusted to change the deposition rate so as to form a closed space in the isolation film 31.

[0137] In the embodiment of the present application, when the isolation film 31 with a closed space is formed on the groove wall and the groove opening of the bit line isolation groove T21 by using the chemical vapor deposition process, the deposition rate of the isolation film 31 is not specifically limited. In some embodiments, when the isolation film 31 with a closed space is formed on the groove wall and the groove opening of the bit line isolation groove T21 by using the chemical vapor deposition process, the deposition rate of the isolation film 31 can be greater than 7nm / min; for example, the deposition rate of the isolation film 31 can be 7nm / min, 8nm / min, 9nm / min or 10nm / min, etc.

[0138] In addition, the present embodiment of the present application does not specifically limit the constituent material of the isolation film 31. As an example, the constituent material of the isolation film 31 may include but is not limited to silicon oxide.

[0139] In some embodiments, step S100 provides a substrate 1 and may further include the following steps S150 to S160 .

[0140] In step S150, if Fig.10 Figure (a) and Fig.10 As shown in FIG. 2( b ), an isolation layer 12 covering the bit line 2 and the isolation film 31 is formed on the side of the bit line 2 and the isolation film 31 away from the growth substrate 111 .

[0141] In some embodiments, the isolation layer 12 and the isolation film 31 may be formed by the same deposition process.

[0142] In step S160, if Fig.11 Figure (a) and Fig.11 As shown in FIG. (b) of FIG. 1 , the structure obtained after forming the isolation layer 12 is turned over, and Fig.12 Figure (a) and Fig.12 As shown in FIG. 2( b ), the isolation layer 12 is bonded to the second substrate 13 .

[0143] In the method for preparing the semiconductor structure provided in the above embodiment, step S200 of etching the substrate to form a plurality of first isolation trenches and a plurality of second isolation trenches may be performed after step S160 of laminating the isolation layer 12 to the second substrate 13 .

[0144] The embodiment of the present application does not specifically limit the method of attaching the isolation layer 12 to the second substrate 13 in step S160. As an example, the isolation layer 12 may be attached to the second substrate 13 by, but not limited to, a bonding process or an adhesive process.

[0145] Please continue reading Fig.12 Figure (a) and Fig.12 As shown in FIG. 5( b ), in some embodiments, step S100 provides a substrate 1 and may further include the following step: forming an epitaxial layer 112 on a surface of the growth base 111 away from the isolation layer 12 .

[0146] In the method for preparing the semiconductor structure provided in the above embodiment, the growth substrate 111 and the epitaxial layer 112 together constitute the first substrate 11 , and the first substrate 11 , the isolation layer 12 and the second substrate 13 together constitute the substrate 1 .

[0147] See also Figures 13 to 15 In step S200 , the substrate 1 is etched to form a plurality of first isolation trenches T11 and a plurality of second isolation trenches T12 .

[0148] The first isolation trench T11 extends along a first direction (e.g., aa' direction) and is located above the corresponding air gap structure 3; the second isolation trench T12 extends along a second direction (e.g., cc' direction). The plurality of first isolation trenches T11 and the plurality of second isolation trenches T12 together isolate a plurality of active pillars 10 arranged in an array. The plurality of active pillars 10 are arranged in a row along the first direction (e.g., aa' direction), and the bit lines 2 connect the active pillars 10 in the same row in series in sequence.

[0149] In some embodiments, step S200 etches the substrate 1 to form a plurality of first isolation trenches T11 and a plurality of second isolation trenches T12 , which may be specifically performed by etching the epitaxial layer 112 and the growth substrate 111 to form the first isolation trenches T11 and the second isolation trenches T12 .

[0150] In the method for manufacturing the semiconductor structure provided in the above embodiment, the air gap structure 3 is located at the bottom of the first isolation trench T11 .

[0151] The active pillar 10 may include a first portion 101 isolated in the growth substrate 111 by the first isolation trench T11 and the second isolation trench T12 , and a second portion 102 isolated in the epitaxial layer 112 by the first isolation trench T11 and the second isolation trench T12 .

[0152] The embodiment of the present application does not specifically limit the method for forming the plurality of first isolation trenches T11 and the plurality of second isolation trenches T12 in step S200. As an example, a self-aligned double patterning (SADP) process may be used to etch the substrate 1 to form the plurality of first isolation trenches T11 and the plurality of second isolation trenches T12. Specifically, the process may include but is not limited to the following steps:

[0153] like Fig.13 Figure (a) and Fig.13 As shown in FIG. (b), a first silicon oxide (SiO2) layer 2A, a polysilicon (Poly) layer 2B, a first silicon oxynitride (SiON) layer 2C, a spin-on hard mask (SOH) layer 2D, and a second silicon oxynitride layer 2E are sequentially deposited on the surface of one side of the substrate 1 by a deposition process. It can be understood that in the embodiment of the present application, the spin-on hard mask layer 2D can be formed by a spin coating process; for example, the spin-on hard mask layer 2D can be a hydrocarbon (C x H y ) system, which may include silicon hard mask materials, carbon hard mask materials, and organic hard mask materials. The first silicon oxide layer 2A, the polysilicon layer 2B, the first silicon oxynitride layer 2C, the spin-on hard mask layer 2D, and the second silicon oxynitride layer 2E may together constitute a mask structure for etching the substrate 1.

[0154] like Fig.14 Figure (a) and Fig.14 As shown in FIG. 2( b), the substrate 1 is first etched based on the mask structure to form a plurality of first isolation trenches T11 extending along a first direction (e.g., aa' direction) in the substrate 1. As an example, in the process of etching to form the first isolation trenches T11, the isolation film 31 can be used as an etching stop layer in the first etching process.

[0155] like Fig.15 Figure (a) and Fig.15 As shown in FIG. 2 (b), the substrate 1 is etched for the second time to form a plurality of second isolation trenches T12 extending along a second direction (e.g., cc' direction) in the substrate 1. As an example, during the process of etching to form the second isolation trenches T12, the bit line 2 can be used as an etching stop layer during the second etching process.

[0156] As an example, the active pillar 10 may be formed with a channel region.

[0157] See also Figures 16 to 22 In some embodiments, after forming a plurality of first isolation trenches T11 and a plurality of second isolation trenches T12 in step S200 , the method for preparing the semiconductor structure may further include the following step: forming a gate dielectric layer 4 .

[0158] Specifically, the gate dielectric layer 4 at least conformally covers the sidewalls of the channel region of the active pillar 10 .

[0159] The embodiment of the present application does not specifically limit the method for forming the gate dielectric layer 4. As an example, the gate dielectric layer 4 may be formed by, but not limited to, the following steps:

[0160] like Fig.16 Figure (a) and Fig.16 As shown in FIG. 7 (b), a first gate dielectric material layer 41 is formed; the first gate dielectric material layer 41 fills the first isolation trench T11 and covers the top surface of the active pillar 10 and the sidewall of the active pillar 10 in the first direction (eg, the aa' direction).

[0161] like Fig.17 Figure (a) and Fig.17 As shown in FIG. 2( b ), a first isolation dielectric material layer 6 ′ is formed; the first isolation dielectric material layer 6 ′ fills the second isolation trench T12 and covers the top surface of the first gate dielectric material layer 41. The first isolation dielectric material layer 6 ′ may be made of, for example, silicon nitride (SiN).

[0162] like Fig.18 Figure (a) and Fig.18 As shown in FIG. (b), a portion of the height of the first gate dielectric material layer 41 is removed so that the top surface of the retained first gate dielectric material layer 41 is not higher than the top surface of the active pillar 10, and the retained first gate dielectric material layer 41 serves as the second gate dielectric material layer 42; and a portion of the height of the first isolation dielectric material layer 6' is removed so that the top surface of the retained first isolation dielectric material layer 6' is also not higher than the top surface of the active pillar 10, and the retained first isolation dielectric material layer 6' serves as the first isolation dielectric layer 6. Optionally, a chemical mechanical polishing (CMP) process may be used but is not limited to remove the aforementioned portion of the height of the first gate dielectric material layer 41 and the portion of the height of the first isolation dielectric material layer 6'.

[0163] like Fig.19 Figure (a) and Fig.19 As shown in FIG. 8( b ), a portion of the second gate dielectric material layer 42 is removed to expose the top of the active pillar 10 , and the remaining second gate dielectric material layer 42 is used as the third gate dielectric material layer 43 .

[0164] like Fig. 20 Figure (a) and Fig. 20 As shown in FIG. 1( b ), a spacer mask layer 7 is formed; the spacer mask layer 7 can cover the sidewalls of the top ends of the active pillars 10 that are exposed. The material of the spacer mask layer 7 can be, for example, silicon nitride.

[0165] like Fig.21 Figure (a) and Fig.21 As shown in FIG. 7 (b), a portion of the third gate dielectric material layer 43 formed on the side wall of the active pillar 10 in the first direction (e.g., the aa' direction) is removed based on the sidewall mask layer 7 to expose the channel region 10A of the active pillar 10 in the first direction (e.g., the aa' direction); and the third gate dielectric material layer 43 formed on the side wall of the active pillar 10 in the second direction (e.g., the cc' direction) is removed.

[0166] like Fig. 22 Figure (a) and Fig. 22 As shown in FIG. 1 (b), the active pillar 10 is etched to form a receiving groove on two opposite sides of the channel region 10A in a first direction (e.g., aa' direction); and the inner wall of the receiving groove is conformally covered with a fourth gate dielectric material layer 44. The third gate dielectric material layer 43 and the fourth gate dielectric material layer 44 together constitute the gate dielectric layer 4. In some possible embodiments, the fourth gate dielectric material layer 44 may also cover the top surface of the active pillar 10.

[0167] See also Fig.23 Figure (a) and Fig.23 As shown in FIG. 5( b ), in some embodiments, after forming the gate dielectric layer 4 , the method for preparing the semiconductor structure may further include the following steps: forming a plurality of gates 5 , wherein the gates 5 cover the channel region 10A of the active pillar 10 .

[0168] Specifically, the gate 5 is formed on a surface of the gate dielectric layer 4 away from the active pillar 10 .

[0169] The present embodiment does not specifically limit the material of the gate 5. As an example, the material of the gate 5 may include at least one of tungsten (W) metal and copper metal.

[0170] In some embodiments, the method for preparing the semiconductor structure may further include the following steps: forming a plurality of word lines arranged at intervals. Each of the word lines extends along a second direction (eg, cc' direction). Each of the word lines sequentially connects the gates 5 in the same column.

[0171] In some embodiments, the active pillar 10 may further include a connecting terminal 10B located at a side of the channel region 10A away from the bit line 2 .

[0172] It can be understood that after forming the gate 5 covering the channel region 10A of the active pillar 10, the sidewall of the connecting end 10B of the active pillar 10 in the second direction (eg, the cc' direction) is still exposed. Fig.24 Figure (a) and Fig.24In FIG. (b), in some embodiments, after forming a plurality of gates 5, the method for preparing the semiconductor structure may further include the following steps: forming a filling dielectric layer 8; the filling dielectric layer 8 is at least filled between the connecting ends 10B of the adjacent active pillars 10 in the second direction (for example, the cc' direction). In some possible embodiments, the top surface of the filling dielectric layer 8 may be flush with the fourth gate dielectric material layer 44 covering the top surface of the active pillar 10.

[0173] See also Fig.25 Figure (a) and Fig.25 In FIG. 5( b ), in some embodiments, after forming the filling dielectric layer 8 , the method for preparing the semiconductor structure may further include the following step: forming a protective layer 9 on the top surface of the obtained structure.

[0174] In the method for preparing the semiconductor structure provided in the above embodiment, the protective layer 9 can be used to protect the underlying structure from the influence of the external environment, provide a certain mechanical strength and corrosion resistance, and prevent external moisture, oxidants and other harmful substances from corroding and damaging the underlying structure, thereby improving the production yield of the preparation method and the reliability of the obtained semiconductor structure.

[0175] It should be noted that the preparation methods of the semiconductor structures provided in the embodiments of the present application can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.

[0176] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0177] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate; the substrate has a plurality of first isolation grooves and a plurality of second isolation grooves, the first isolation grooves extend along a first direction, the second isolation grooves extend along a second direction, the first direction and the second direction are parallel to the substrate and intersect; The plurality of first isolation trenches and the plurality of second isolation trenches together isolate a plurality of active pillars arranged in an array; The plurality of active pillars are arranged in a row along the first direction; a plurality of spaced-apart bit lines; The bit line is located below the active pillars and extends along the first direction to sequentially connect the active pillars in the same row in series; A plurality of air gap structures; the air gap structures are located between adjacent bit lines and at the bottom of the corresponding first isolation trench.

2. The semiconductor structure according to claim 1, characterized in that: The air gap structure comprises: An isolation film covers the sidewalls of the adjacent bit lines and forms a closed space; and an isolation air gap located within the enclosed space.

3. The semiconductor structure according to claim 1 or 2, characterized in that: A dimension of the air gap structure in a direction perpendicular to the substrate is greater than or equal to a dimension of the bit line in a direction perpendicular to the substrate.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The substrate comprises: a first base, an isolation layer and a second base which are stacked; wherein The active pillar, the bit line and the air gap structure are all located in the first substrate, and the bit line and the air gap structure are also located on a surface of the isolation layer away from the second substrate, and the active pillar is also located on a surface of the bit line away from the isolation layer.

5. The semiconductor structure according to claim 4, characterized in that: The first substrate comprises: a growth substrate and an epitaxial layer epitaxially grown on the surface of the growth substrate; wherein, The bit line and the air gap structure are located on a surface of the growth substrate away from the epitaxial layer; The active pillar includes a first portion isolated by the first isolation trench and the second isolation trench in the growth substrate, and a second portion isolated by the first isolation trench and the second isolation trench in the epitaxial layer.

6. The semiconductor structure according to claim 4, characterized in that: The isolation layer and the isolation film in the air gap structure are an integrated structure.

7. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A plurality of bit lines extending along a first direction and arranged at intervals in a second direction are formed in the substrate, wherein the first direction and the second direction are parallel to and intersect the substrate; An air gap structure is formed between the bit lines adjacent to each other in the second direction; Etching the substrate to form a plurality of first isolation trenches and a plurality of second isolation trenches; The first isolation trench extends along the first direction and is located above the corresponding air gap structure; The second isolation trench extends along the second direction; The plurality of first isolation trenches and the plurality of second isolation trenches together isolate a plurality of active pillars arranged in an array; the plurality of active pillars are arranged in a row along the first direction, and the bit lines connect the active pillars in the same row in series in sequence.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The providing of a substrate comprises: Providing a growth substrate; forming a bit line material layer on a surface of one side of the growth substrate; forming a plurality of bit line isolation grooves penetrating the bit line material layer and extending into the growth substrate; the bit line isolation grooves extending along the first direction, the plurality of bit line isolation grooves separating the bit line material layer into a plurality of bit lines; An isolation film with a closed space is formed on the groove wall and the groove opening of the bit line isolation groove, and an isolation air gap is formed in the closed space; the air gap structure includes the isolation film and the isolation air gap.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step of forming a bit line material layer on a surface of one side of the growth substrate comprises: forming an initial bit line material layer on a surface of one side of the growth substrate; The initial bit line material layer is subjected to metal silicidation treatment by adopting a rapid thermal annealing process to form the bit line material layer.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The isolation film having the closed space is formed on the groove wall and the groove opening of the bit line isolation groove by using a chemical vapor deposition process; the deposition rate of the isolation film is greater than 7nm / min.

11. The method for preparing a semiconductor structure according to claim 8, characterized in that: The providing of the substrate further comprises: forming an isolation layer covering the bit line and the isolation film on a side of the bit line and the isolation film away from the growth substrate; flipping the structure obtained after forming the isolation layer, and attaching the isolation layer to a second substrate; The etching of the substrate to form a plurality of first isolation grooves and a plurality of second isolation grooves is performed after the isolation layer is attached to the second base.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The isolation layer and the isolation film are formed by adopting the same deposition process.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that: The providing of the substrate further comprises: An epitaxial layer is formed on a surface of the growth substrate away from the isolation layer; the growth substrate and the epitaxial layer together constitute a first substrate; the substrate includes the first substrate, the isolation layer and the second substrate; The etching of the substrate to form a plurality of first isolation trenches and a plurality of second isolation trenches comprises: The epitaxial layer and the growth substrate are etched to form the first isolation trench and the second isolation trench; the air gap structure is located at the bottom of the first isolation trench; the active column includes: a first part isolated by the first isolation trench and the second isolation trench in the growth substrate, and a second part isolated by the first isolation trench and the second isolation trench in the epitaxial layer.

14. The method for preparing a semiconductor structure according to claim 7, characterized in that: After forming a plurality of the first isolation trenches and a plurality of the second isolation trenches, the method for preparing the semiconductor structure further includes: forming a gate dielectric layer that conformally covers at least the sidewalls of the channel region of the active pillar; A gate is formed to cover the channel region of the active pillar.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The forming of a gate dielectric layer that at least conformally covers the sidewall of the channel region of the active pillar comprises: forming a first gate dielectric material layer; the first gate dielectric material layer is filled in the first isolation trench and covers the top surface of the active column and the sidewall of the active column in the first direction; forming a first isolation dielectric material layer; the first isolation dielectric material layer is filled in the second isolation groove and covers the top surface of the first gate dielectric material layer; Removing a portion of the first gate dielectric material layer so that the top surface of the retained first gate dielectric material layer is not higher than the top surface of the active pillar; the retained first gate dielectric material layer is used as the second gate dielectric material layer; and removing a portion of the first isolation dielectric material layer so that the top surface of the retained first isolation dielectric material layer is not higher than the top surface of the active pillar; the retained first isolation dielectric material layer is used as the first isolation dielectric layer; Removing a portion of the height of the second gate dielectric material layer to expose the top of the active pillar; the remaining second gate dielectric material layer is used as a third gate dielectric material layer; Forming a sidewall mask layer; the sidewall mask layer covers the sidewall of the exposed top of the active column; Based on the sidewall mask layer, a portion of the third gate dielectric material layer formed on the sidewall of the active pillar in the first direction is removed to expose the channel region of the active pillar in the first direction; and the third gate dielectric material layer formed on the sidewall of the active pillar in the second direction is removed; The active pillar is etched to form a receiving groove on two opposite sides of the channel region in the first direction; and the inner wall of the receiving groove is conformally covered with the fourth gate dielectric material layer; the third gate dielectric material layer and the fourth gate dielectric material layer together constitute the gate dielectric layer.

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