Display panel and spliced ​​display device

Abstract

The embodiment of the present invention provides a display panel and a spliced ​​display device, which relate to the field of display technology to weaken visual seams. The display panel includes: a first edge and a second edge opposite to each other; a first pixel row and a second pixel row, the first pixel row is adjacent to the first edge, and includes a plurality of first sub-pixels arranged along the second direction, the first sub-pixels include a first light-emitting device and a first pixel circuit, the second pixel row includes a plurality of second sub-pixels arranged along the second direction, the second sub-pixels include a second light-emitting device and a second pixel circuit; a first spacing area corresponding to the second pixel row, the first spacing area is located on the side of the second pixel row corresponding to it close to the first edge, and the first spacing area is adjacent to the second pixel row corresponding to it; the second pixel row includes a second A pixel row adjacent to the first pixel row, the first pixel circuit is located in the first spacing area corresponding to the second A pixel row, and the second pixel circuit is located on the side of the second light-emitting device close to the first edge.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a spliced ​​display device. [Background technology]

[0002] For display panels with borders, when they are used in large-size spliced ​​display devices, the light-emitting areas of adjacent display panels will be separated by at least two border widths, resulting in obvious visual seams when the spliced ​​display device displays images, seriously affecting the display effect. [Summary of the invention]

[0003] In view of this, an embodiment of the present invention provides a display panel and a spliced ​​display device to reduce visual seams.

[0004] In one aspect, an embodiment of the present invention provides a display panel, including:

[0005] a first edge and a second edge disposed opposite to each other in a first direction;

[0006] A plurality of pixel rows arranged along the first direction, the pixel rows comprising a first pixel row and a plurality of second pixel rows, wherein the first pixel row is adjacent to the first edge, the first pixel row comprises a plurality of first sub-pixels arranged along the second direction, the first sub-pixels comprise electrically connected first light-emitting devices and first pixel circuits, the second pixel row comprises a plurality of second sub-pixels arranged along the second direction, the second sub-pixels comprise electrically connected second light-emitting devices and second pixel circuits, and the first direction intersects the second direction;

[0007] a plurality of first spacing regions corresponding one to the plurality of second pixel rows, wherein the first spacing regions are located on a side of the corresponding second pixel row close to the first edge, and the first spacing regions are adjacent to the corresponding second pixel row;

[0008] Among them, the second pixel row includes a second A pixel row adjacent to the first pixel row, the first pixel circuit is located on the side of the first light-emitting device away from the first edge, and the first pixel circuit is located in the first spacing area corresponding to the second A pixel row, and the second pixel circuit is located on the side of the second light-emitting device close to the first edge.

[0009] On the other hand, an embodiment of the present invention provides a spliced ​​display device, comprising n display panels as described above, wherein at least two of the display panels are spliced ​​along the first direction, and n≥2.

[0010] One of the above technical solutions has the following beneficial effects:

[0011] In the embodiment of the present invention, by moving the first pixel circuit in the first sub-pixel from the outside of the first light-emitting device (the side close to the first edge) to the first spacing area on the inside of the first light-emitting device (the side away from the first edge), it is equivalent to releasing the space originally occupied by the first pixel circuit on the outside of the first light-emitting device. In this way, the peripheral wiring and peripheral circuit structures on the outside of the first light-emitting device can also be moved toward the first light-emitting device. Then, when cutting the display panel, the distance between the cutting line (first edge) corresponding to the upper frame and the first pixel row can be adjusted to reduce it, thereby narrowing the width of the upper frame of the display panel.

[0012] After narrowing the upper frame of the display panel, when the display panel is used in a spliced ​​display device, for two adjacent display panels in the first direction, the sum of the widths occupied by the lower frame of the previous display panel and the upper frame of the next display panel can be reduced, that is, the difference between the spacing m1 between the second light-emitting device of the last second pixel row in the previous display panel and the first light-emitting device of the first pixel row in the next display panel and the spacing m2 between the light-emitting devices in any other two adjacent pixel rows is reduced, thereby making the light-emitting devices in the entire spliced ​​display device tend to be arranged at equal intervals, weakening the visual seams, and achieving seamless splicing between display panels. Moreover, after narrowing the width of the upper frame of the display panel, in an optional setting, the narrowed width of the upper frame can also be compensated to the lower frame. For example, if the width n1 of the upper frame is narrowed, the width n1 can be fully compensated to the lower frame, so that the width of the lower frame increases by n1, or only the width n2 of the lower frame can be compensated, n2<n1, so as to increase the width of the lower frame of the display panel without changing the design size of the display panel or reducing the design size of the display panel, thereby providing a larger setting space for the pins, avoiding the pins and fan-out wiring from being too densely arranged, and effectively avoiding signal interference. Of course, if the lower frame of the display panel already has enough space to accommodate the pins, the width of the lower frame of the display panel can be left unchanged, and only the upper frame of the display panel can be narrowed to better eliminate the visual seams.

[0013] In summary, by adopting the technical solution provided in the embodiment of the present invention, when the display panel is applied to a spliced ​​display device, seamless splicing can be achieved, visual seams can be eliminated, and the display effect of the spliced ​​display device can be optimized. In addition, sufficient setting space can be provided for the pins without increasing the design size of the display panel, thereby reducing signal interference.

Brief Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A top view of a display panel in the related art;

[0016] Figure 2 A top view of a spliced ​​display device in the related art;

[0017] Figure 3 A top view of a display panel provided by an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 5 A top view of a spliced ​​display device provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of a connection between a display panel and a circuit board provided in an embodiment of the present invention;

[0021] Figure 7 Another schematic diagram of connection between a display panel and a circuit board provided by an embodiment of the present invention;

[0022] Figure 8 A schematic diagram of a circuit structure of a first sub-pixel provided in an embodiment of the present invention;

[0023] Fig. 9 A schematic diagram of a film layer structure of a first sub-pixel provided in an embodiment of the present invention;

[0024] Fig.10 A timing diagram corresponding to the first pixel circuit provided in an embodiment of the present invention;

[0025] Fig.11 Another top view of the display panel provided by the embodiment of the present invention;

[0026] Fig.12 A schematic diagram of another film layer structure of a first sub-pixel provided in an embodiment of the present invention;

[0027] Fig.13 A schematic diagram of another film layer structure of the first sub-pixel provided in an embodiment of the present invention;

[0028] Fig.14Another top view of the display panel provided by the embodiment of the present invention;

[0029] Fig.15 A schematic diagram of a setting position of a shift register provided in an embodiment of the present invention;

[0030] Fig.16 for Fig.12 A cross-sectional view along the A1-A2 direction;

[0031] Fig.17 Another top view of the display panel provided by the embodiment of the present invention;

[0032] Fig.18 A schematic diagram of a setting position of a gating circuit provided in an embodiment of the present invention;

[0033] Fig.19 A schematic diagram of a structure of a gating circuit provided by an embodiment of the present invention;

[0034] Fig. 20 Another top view of the display panel provided by the embodiment of the present invention;

[0035] Fig.21 Another top view of the spliced ​​display device provided by an embodiment of the present invention;

[0036] Fig. 22 Another top view of the display panel provided by the embodiment of the present invention;

[0037] Fig.23 Another top view of the display panel provided by the embodiment of the present invention;

[0038] Fig.24 A schematic diagram of the structure of a spliced ​​display device provided by an embodiment of the present invention;

[0039] Fig.25 Another structural schematic diagram of a spliced ​​display device provided by an embodiment of the present invention. [Specific implementation method]

[0040] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0043] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0044] like Figure 1 As shown, Figure 1 It is a top view of a display panel 101 in the related art, wherein the display panel 101 includes a plurality of pixel rows 102 arranged along a first direction x and a plurality of pins 103 located in a lower frame of the display panel 101, wherein the pins 103 are used to provide a driving signal to a sub-pixel 104 in the pixel row 102, so as to realize normal display of the display panel 101. Exemplarily, the pins 103 may be electrically connected to the data line Data through a fan-out wiring 105, and further provide a data signal to the sub-pixel 104 in the pixel row 102.

[0045] The inventors have found that in order to provide sufficient space for the pins 103, the lower frame of the display panel 101 is usually widened in the relevant design. However, when the display panel 101 is used in a large-sized spliced ​​display device, Figure 2 As shown, Figure 2 This is a top view of a spliced ​​display device in the related art. For two adjacent display panels 101 in the first direction x, the last pixel row 102 in the previous display panel 101 and the first pixel row 102 in the next display panel 101 are spaced far apart, resulting in a spacing m1 between two adjacent pixel rows 102 in different display panels 101 being significantly greater than a spacing m2 between two adjacent pixel rows 102 in the same display panel 101. In this way, when the spliced ​​display device displays images, there will be obvious visual seams between the two display panels 101, resulting in an uneven display effect.

[0046] Considering that the fan-out trace 105 and the edge chamfer also occupy a part of the lower frame space, if the visual seam is weakened by simply compressing the width of the lower frame, the setting space of the fan-out trace 105 and the pin 103 will be very small, which will not only make the wiring design difficult, but also easily lead to signal interference problems.

[0047] In this regard, an embodiment of the present invention provides a display panel, which may specifically be a light emitting diode (LED) display panel, for example, a mini LED display panel or a micro LED display panel.

[0048] like Figure 3 and Figure 4 As shown, Figure 3 A top view of the display panel 100 provided in an embodiment of the present invention. Figure 4 A schematic diagram of a film layer structure of a display panel 100 provided in an embodiment of the present invention, wherein the display panel 100 includes a first edge 1 and a second edge 2 arranged opposite to each other in a first direction x, and a plurality of pixel rows 3 arranged along the first direction x. The pixel rows 3 include a first pixel row 31 and a plurality of second pixel rows 32, wherein the first pixel row 31 is adjacent to the first edge 1, that is, the first pixel row 31 is the pixel row 3 closest to the first edge 1 among the plurality of pixel rows 3, and the second pixel rows 32 are the other pixel rows 3 except the first pixel row 31.

[0049] The first pixel row 31 includes a plurality of first sub-pixels 4 arranged along the second direction y, the first sub-pixels 4 include electrically connected first light-emitting devices 41 and first pixel circuits 42, the second pixel row 32 includes a plurality of second sub-pixels 5 arranged along the second direction y, the second sub-pixels 5 include electrically connected second light-emitting devices 51 and second pixel circuits 52, wherein the first light-emitting devices 41 and the second light-emitting devices 51 can be mini LEDs or micro LEDs, and the first direction x intersects with the second direction y.

[0050] The display panel 100 further includes a plurality of first spacing regions 7 corresponding to the plurality of second pixel rows 32 one by one, the first spacing regions 7 being located on a side of the second pixel row 32 corresponding thereto close to the first edge 1, and the first spacing regions 7 are adjacent to the second pixel row 32 corresponding thereto. In one configuration, the first spacing regions 7 corresponding to different second pixel rows 32 have the same width in the first direction x, so as to achieve equal spacing arrangement of the second light emitting devices 51 in different second pixel rows 32.

[0051] The second pixel row 32 includes a second A pixel row 321 adjacent to the first pixel row 31. The first pixel circuit 42 is located on a side of the first light emitting device 41 away from the first edge 1, and the first pixel circuit 42 is located in the first spacing area 7 corresponding to the second A pixel row 321, and the second pixel circuit 52 is located on a side of the second light emitting device 51 close to the first edge 1.

[0052] It should be noted that, in the embodiment of the present invention, the first edge 1 and the second edge 2 are two opposite cutting edges of the display panel 100 in the first direction x, that is, the outermost edges of the display panel 100. In the embodiment of the present invention, the part of the border between the first edge 1 and the edge of the first pixel row 31 is called the upper border, and the part of the border between the second edge 2 and the edge of the second pixel row 32 closest to it is called the lower border.

[0053] In addition, the display panel 100 further includes a pin 6 located at the lower frame, the pin 6 is close to the second edge 2, and the pin 6 is used to provide a driving signal to the first sub-pixel 4 and the second sub-pixel 5 to drive the display panel 100 to emit light normally.

[0054] In the structural design of a conventional display panel, the arrangement of pixel circuits in different sub-pixels is consistent, that is, the pixel circuits in each sub-pixel are located on the same side of the light-emitting device electrically connected thereto. However, the embodiment of the present invention makes a differentiated design for the arrangement position of the first pixel circuit 42 in the first sub-pixel 4 and the arrangement position of the second pixel circuit 52 in the second sub-pixel 5.

[0055] In the embodiment of the present invention, by moving the first pixel circuit 42 in the first sub-pixel 4 from the outside of the first light-emitting device 41 (the side close to the first edge 1) to the first spacer 7 on the inside of the first light-emitting device 41 (the side away from the first edge 1), it is equivalent to releasing the space originally occupied by the first pixel circuit 42 on the outside of the first light-emitting device 41. In this way, the peripheral wiring and peripheral circuit structures on the outside of the first light-emitting device 41 can also be moved toward the first light-emitting device 41. Then, when cutting the display panel 100, the distance between the cutting line (first edge 1) corresponding to the upper frame and the first pixel row 31 can be adjusted to reduce it, thereby narrowing the width of the upper frame of the display panel 100.

[0056] After the upper frame of the display panel 100 is narrowed, when the display panel 100 is used in a spliced ​​display device, Figure 5 As shown, Figure 5A top view of a spliced ​​display device provided by an embodiment of the present invention, for two adjacent display panels 100 in the first direction x, the sum of the widths of the lower frame of the previous display panel 100 and the upper frame of the next display panel 100 can be reduced, that is, the difference between the spacing m1 between the second light-emitting device 51 of the last second pixel row 32 in the previous display panel 100 and the first light-emitting device 41 of the first pixel row 31 in the next display panel 100 and the spacing m2 between the light-emitting devices in any other two adjacent pixel rows 3 is reduced, so that the light-emitting devices in the entire spliced ​​display device tend to be arranged at equal intervals, weakening the visual seams and achieving seamless splicing between the display panels 100. Moreover, after narrowing the width of the upper frame of the display panel 100, in an optional setting, the narrowed width of the upper frame can also be compensated to the lower frame. For example, if the width n1 of the upper frame is narrowed, the width n1 can be fully compensated to the lower frame, so that the width of the lower frame increases by n1, or only the width n2 of the lower frame can be compensated, n2<n1, so as to increase the width of the lower frame of the display panel 100 without changing the design size of the display panel 100 or reducing the design size of the display panel 100, thereby providing a larger setting space for the pin 6, avoiding the pin 6 and the fan-out wiring from being arranged too densely, and effectively avoiding signal interference. Of course, if the lower frame of the display panel 100 already has enough space to accommodate the pin 6, the width of the lower frame of the display panel 100 can be left unchanged, and only the upper frame of the display panel 100 can be narrowed to better eliminate the visual seams.

[0057] In summary, by adopting the technical solution provided in the embodiment of the present invention, when the display panel 100 is applied to a spliced ​​display device, seamless splicing can be achieved, visual seams can be eliminated, and the display effect of the spliced ​​display device can be optimized. In addition, sufficient setting space can be provided for the pin 6 without increasing the design size of the display panel 100, thereby reducing signal interference.

[0058] It should be noted that the embodiment of the present invention does not place the first pixel circuit 42 inside the first light-emitting device 41 by exchanging the positions of the first pixel circuit 42 and the first light-emitting device 41. The embodiment of the present invention provides a first spacer 7 between the pixel rows 3 to accommodate the first pixel circuit 42 after adjusting its position. In an optional setting, the embodiment of the present invention does not change the position of the first light-emitting device 41, but only adjusts the position of the first pixel circuit 42.

[0059] Moreover, it should be noted that the current size specifications of mini LED and micro LED are very small, so a lot of sub-pixels can be arranged in a unit area. Even if a first spacing area 7 is arranged between pixel rows 3, and the first spacing area 7 has a width that can accommodate the first pixel circuit 42, it is also possible to ensure that the display panel 100 has a high pixel density (Pixels Per Inch, PPI), for example, the PPI of the display panel 100 can be between 80 and 100. In other words, the current spliced ​​display devices are mostly large-sized LED spliced ​​screens, movie screens, long-distance viewing electronic devices and other products. Such display devices do not have very high requirements for pixel density (Pixels Per Inch, PPI), and the requirements for PPI of such display devices are generally much lower than the requirements for PPI of display devices such as mobile phones and computers. Therefore, even if the display panel 100 provided in the embodiment of the present invention has a first spacing area 7 between pixel rows 3, it can meet the requirements of the spliced ​​display device for PPI.

[0060] In one possible implementation, see again Figure 3 , the distance between the first edge 1 and the edge of the first light-emitting device 41 (hereinafter referred to as the distance between the first edge 1 and the first light-emitting device 41) is L1, the distance between the second edge 2 and the edge of the second light-emitting device 51 closest thereto (hereinafter referred to as the distance between the second edge 2 and the second light-emitting device 51 closest thereto) is L2, L2>L1. The edge of the above-mentioned light-emitting device can be understood as the edge of the positive projection of the light-emitting device in the direction perpendicular to the plane where the display panel 100 is located.

[0061] By adjusting the position of the first pixel circuit 42 to achieve the narrowing of the width of the upper frame, the width of the upper frame can be smaller than the width of the lower frame. When the display panel 100 is used in a spliced ​​display device, the narrowed width of the upper frame can be used to reduce the above-mentioned spacing m1, so that it is consistent with the spacing m2, so as to better achieve seamless splicing. In addition, if you want to further optimize the wiring design of the pin 6 and the fan-out wiring in the lower frame, you can also compensate at least part of the narrowed width of the upper frame to the lower frame, so that the lower frame can be widened without increasing the design size of the display panel 100, thereby providing a larger setting space for the pin 6 and the fan-out wiring.

[0062] In a possible implementation, Figure 6 As shown, Figure 6A connection diagram of the display panel 100 and the circuit board 300 provided in an embodiment of the present invention, the display panel 100 further includes a pin 6, the pin 6 is located on the side close to the second edge 2, the pin 6 is electrically connected to one end of the side trace 90, the side trace 90 is bent to the backlight side of the display panel 100, and the other end of the side trace 90 is used to be electrically connected to the circuit board 300. Among them, the circuit board 300 is located on the backlight side of the display panel 100, and is used to provide the display panel 100 with a variety of signals to drive its display, and the circuit board 300 can be a printed circuit board (Flexible Printed Circuit, FPC), a chip on film (Chip On Film, COF) or a transfer printed circuit board, etc.

[0063] In the traditional setting, Figure 7 As shown, Figure 7 Another connection diagram of the display panel 100 and the circuit board 300 provided in an embodiment of the present invention is that the pin 6 of the display panel 100 is usually directly bound to the circuit board pin of the circuit board 300, and then the circuit board 300 is bent to the backlight side of the display panel 100. In this way, the pin 6 of the display panel 100 needs to be in contact with the circuit board pin of the circuit board 300 for binding. To improve the binding reliability, the pin 6 needs to have a larger area. For example, the size of the pin 6 in the first direction x is generally between 400μm and 700μm, which results in the pin 6 needing to occupy a larger area at the lower frame.

[0064] In the embodiment of the present invention, the pin 6 of the display panel 100 is electrically connected to the circuit board 300 by using the side wiring 90. Compared with the contact binding between the pin 6 and the circuit board pin, when the pin 6 is in contact with the side wiring 90, the pin 6 only needs to have a smaller area to achieve higher connection reliability. For example, in this setting mode, the size of the pin 6 in the first direction x only needs to be between 50μm and 80μm.

[0065] Therefore, this arrangement can significantly reduce the design area of ​​the pin 6, thereby saving the space required for the pin 6 in the lower frame. To this end, the embodiment of the present invention can further narrow the width of the lower frame on the premise of narrowing the width of the upper frame, and further reduce the spacing m1 when the display panel 100 is used in a spliced ​​display device to better eliminate visual seams.

[0066] In one possible implementation, see again Figure 4 The display panel 100 further includes a first driving signal line 8 electrically connected to the first pixel circuit 42 , the first driving signal line 8 extends along the second direction y, and the first driving signal line 8 is located in the first spacing area 7 corresponding to the second A pixel row 321 .

[0067] By also setting the first drive signal line 8 electrically connected to the first pixel circuit 42 in the first spacing area 7 corresponding to the second A pixel row 321, on the one hand, it can be avoided that the first drive signal line 8 occupies the outer space of the first light-emitting device 41, and more width that can be cut off on the outer side of the first light-emitting device 41 is released, which helps to narrow the width of the upper frame of the display panel 100 to a greater extent. On the other hand, the first drive signal line 8 and the first pixel circuit 42 are both located in the first spacing area 7 corresponding to the second A pixel row 321, and the connection distance between the first drive signal line 8 and the first pixel circuit 42 is small. The first drive signal line 8 can be directly connected to the first pixel circuit 42, and there is no need to set a connection line that is wound around the side of the first light-emitting device 41, which simplifies the wiring design and releases more wiring space.

[0068] Further, see again Figure 4 The first pixel circuit 42 is electrically connected to the scan signal line Scan, the first positive power signal line PVDD1, the reset signal line Vref and the light emitting control signal line Emit, respectively, wherein the scan signal line Scan may specifically include a first scan signal line Scan1 and a second scan signal line Scan2.

[0069] Among them, the first scan signal line Scan1 extends along the second direction y, and is used to provide the first scan signal to the first pixel circuit 42, the second scan signal line Scan2 extends along the second direction y, and is used to provide the second scan signal to the first pixel circuit 42, the first positive power signal line PVDD1 extends along the second direction y, and is used to provide the positive power signal to the first pixel circuit 42, the reset signal line Vref extends along the second direction y, and is used to provide the reset signal to the first pixel circuit 42, and the light emitting control signal line Emit extends along the second direction y, and is used to provide the light emitting control signal to the first pixel circuit 42. That is, the scan signal line Scan, the first positive power signal line PVDD1, the reset signal line Vref, and the light emitting control signal line Emit all extend along the second direction y, and are all used to provide the driving signal to the first pixel circuit 42.

[0070] In the embodiment of the present invention, the first driving signal line 8 may include at least one of the above-mentioned scan signal line Scan, the first positive power signal line PVDD1, the reset signal line Vref and the light emitting control signal line Emit.

[0071] It should be noted that, in the embodiment of the present invention, the first pixel circuit 42 and the second pixel circuit 52 can both adopt Figure 8 Circuit structure of the pixel circuit. Taking the first pixel circuit 42 as an example, the connection mode and function of each of the first driving signal lines 8 and the working principle of the first pixel circuit 42 are described as follows:

[0072] like Figure 8 and Fig. 9 As shown, Figure 8 A schematic diagram of a circuit structure of a first sub-pixel 4 provided in an embodiment of the present invention, Fig. 9 This is a schematic diagram of a film structure of a first sub-pixel 4 provided in an embodiment of the present invention. The first pixel circuit 42 may specifically include a storage capacitor Cst and a first transistor T1 to a ninth transistor T9.

[0073] Among them, the gates of the fourth transistor T4 and the fifth transistor T5 are respectively electrically connected to the first scan signal line Scan1, the first electrode of the fourth transistor T4 is electrically connected to the reset signal line Vref, the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5, and the second electrode of the fifth transistor T5 is electrically connected to the gate of the third transistor T3.

[0074] The gate of the second transistor T2 is electrically connected to the second scan signal line Scan2, the first electrode of the second transistor T2 is electrically connected to the data line Data, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3; the gates of the sixth transistor T6 and the seventh transistor T7 are electrically connected to the second scan signal line Scan2, respectively, the first electrode of the seventh transistor T7 is electrically connected to the first electrode of the third transistor T3, the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is electrically connected to the gate of the third transistor T3; the gate of the eighth transistor T8 is electrically connected to the second scan signal line Scan2, the first electrode of the eighth transistor T8 is electrically connected to the reset signal line Vref, and the second electrode of the eighth transistor T8 is electrically connected to the first light-emitting device 41.

[0075] The gates of the first transistor T1 and the ninth transistor T9 are electrically connected to the light emitting control signal line Emit, respectively; the first electrode of the first transistor T1 is electrically connected to the first positive power supply signal line PVDD1; the second electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3; the first electrode of the ninth transistor T9 is electrically connected to the second electrode of the third transistor T3; and the second electrode of the ninth transistor T9 is electrically connected to the first light emitting device 41.

[0076] A first plate of the storage capacitor Cst is electrically connected to the first positive power signal line PVDD1 , and a first plate of the second storage capacitor Cst is electrically connected to the gate of the third transistor T3 .

[0077] like Fig.10 As shown, Fig.10 This is a timing diagram corresponding to the first pixel circuit 42 provided in the embodiment of the present invention. The working process of the first pixel circuit 42 includes an initialization period T1, a charging period T2 and a light emitting period T3.

[0078] In the initialization period T1, the first scan signal line Scan1 provides a low level, and the fourth transistor T4 and the fifth transistor T5 write the reset voltage provided by the reset signal line Vref into the gate of the third transistor T3 to initialize the gate potential of the third transistor T3.

[0079] During the charging period T2, the second scan signal line Scan2 provides a low level, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 write the data voltage provided by the data line Data into the gate of the third transistor T3, and perform threshold compensation on the third transistor T3, and the eighth transistor T8 writes the provided reset voltage into the first light-emitting device 41 to initialize the potential of the positive electrode 411 of the first light-emitting device 41.

[0080] In the light-emitting period T3, the light-emitting control signal line Emit provides a low level, and the first transistor T1 and the ninth transistor T9 transmit the driving current converted by the positive power supply voltage provided by the first positive power supply signal line PVDD1 and the data voltage provided by the data line Data to the first light-emitting device 41, driving the first light-emitting device 41 to emit light.

[0081] In addition, it should be noted that see Figure 4 , the display panel 100 may also include a second negative power signal line PVEE2 and a second positive power signal line PVDD2 extending in the first direction x. The second negative power signal line PVEE2 is electrically connected to the first negative power signal line PVEE1, and is used to form a grid structure with the first negative power signal line PVEE1 to reduce the overall routing load of the negative power signal line. Similarly, the second positive power signal line PVDD2 is electrically connected to the first positive power signal line PVDD1, and is used to form a grid structure with the first positive power signal line PVDD1 to reduce the overall routing load of the positive power signal line.

[0082] In a possible implementation, combining Fig. 9 and Fig.11 , Fig.11 Another top view of the display panel 100 provided by the embodiment of the present invention, the positive electrode 411 of the first light-emitting device 41 is electrically connected to the first pixel circuit 42 through the first connecting portion 10, and the negative electrode 412 of the first light-emitting device 41 is electrically connected to the first negative power signal line PVEE1. The positive electrode 411 of the first light-emitting device 41 is located on the side of the negative electrode 412 of the first light-emitting device 41 away from the first pixel circuit 42.

[0083] It should be noted that the first edge 1 of the display panel 100 can be regarded as the upper edge of the display panel 100. The anode 411 of the first light-emitting device 41 is located on the side of the cathode 412 of the first light-emitting device 41 away from the first pixel circuit 42, that is, the anode 411 of the first light-emitting device 41 is closer to the upper edge of the display panel 100, which is consistent with the arrangement of the anode 511 and the cathode 512 in the second light-emitting device 51.

[0084] In the manufacturing process of the display panel 100, the light emitting devices are grown on a growth substrate and then transferred in bulk, wherein the light emitting devices grown on the growth substrate have the same orientation. In the embodiment of the present invention, by setting the arrangement direction of the positive and negative electrodes in the first light emitting device 41 to be consistent with the arrangement direction of the positive and negative electrodes in the second light emitting device 51, it is not necessary to adjust the orientation of the light emitting devices grown in the growth substrate, and it is not necessary to perform operations such as reversing the light emitting devices when the bulk transfer is performed for binding, thereby greatly reducing the complexity of the process.

[0085] In a possible implementation, combining Fig. 9 and Fig.12 , Fig.12 A schematic diagram of another film layer structure of the first sub-pixel 4 provided in an embodiment of the present invention, wherein a first connecting wiring 9 is connected between the first connecting portion 10 and the first pixel circuit 42, the first connecting wiring 9 includes a first wiring segment 91 and a second wiring segment 92 that are connected, an end of the first wiring segment 91 is electrically connected to the first connecting portion 10, at least a portion of the first wiring segment 91 extends along the second direction y, and the second wiring segment 92 extends on one side of the first light-emitting device 41 in the second direction y.

[0086] In an alternative setup, see Fig. 9 , the first wiring segment 91 first protrudes from the outer side of the first light emitting device 41 in the first direction x, and then extends laterally in the second direction y. Alternatively, in another optional configuration, see Fig.12 The first routing segment 91 directly extends laterally along the second direction y. At this time, the first routing segment 91 will not protrude from the outside of the first light-emitting device 41 and occupy additional width in the first direction x, thereby freeing up more space on the outside of the first light-emitting device 41 for cutting, further reducing the width of the upper frame of the display panel 100.

[0087] Furthermore, if Fig.13 As shown, Fig.13 This is another schematic diagram of the film layer structure of the first sub-pixel 4 provided in an embodiment of the present invention. The first wiring segment 91 extends along the second direction y, and the first connecting portion 10 is located on one side of the anode 411 of the first light-emitting device 41 in the second direction y.

[0088] In this arrangement, the first routing segment 91 and the first connecting portion 10 will not protrude from the outside of the first light-emitting device 41 and occupy additional width in the first direction x, thereby releasing more cutting space on the outside of the first light-emitting device 41 and narrowing the upper frame to a greater extent.

[0089] In a possible implementation, Fig.14 As shown, Fig.14 This is another top view of a display panel provided by an embodiment of the present invention. The display panel further includes an electrostatic protection circuit 91 for performing electrostatic protection on the display panel. The electrostatic protection circuit 91 is located between two adjacent first light-emitting devices 41 in the first pixel row 31 .

[0090] In one structure, the electrostatic protection circuit 91 may specifically include a first protection transistor M1 and a second protection transistor M2. The first protection transistor M1 is a P-type transistor, the gate and the first electrode of the first protection transistor M1 are electrically connected to the first fixed potential signal line VGH, and the second electrode of the first protection transistor M1 is electrically connected to the data line Data; the second protection transistor M2 is an n-type transistor, the gate and the first electrode of the second protection transistor M2 are electrically connected to the second fixed potential signal line VGL, and the second electrode of the second protection transistor M2 is electrically connected to the data line Data.

[0091] In the conventional design, the electrostatic protection circuit 91 is generally arranged on the upper frame of the display panel 100, that is, on the side of the first pixel row 31 close to the first edge 1. However, in the embodiment of the present invention, the electrostatic protection circuit 91 is arranged between two adjacent first light-emitting devices 41 in the second pixel row A 31, thereby saving the space required for the electrostatic protection circuit 91 in the upper frame, further freeing up the cutting width of the upper frame.

[0092] Moreover, it should be noted that in the film layer design of the display panel, the second negative power signal line PVEE2 is on the same layer as at least part of the connecting line between the first protection transistor M1 and the first fixed potential signal line VGH, and is on the same layer as at least part of the connecting line between the second protection transistor M2 and the second fixed potential signal line VGL, and the first negative power signal line PVEE1 is on the same layer as the gates of the first protection transistor M1 and the second protection transistor M2.

[0093] For the first light-emitting device 41, if the cathode 412 of the first light-emitting device 41 is located on the side of the anode 411 of the first light-emitting device 41 close to the first edge 1, the first negative power signal line PVEE1 also needs to be located on the outside of the first light-emitting device 41 accordingly, then the second negative power signal line PVEE2, when connected to the first negative power signal line PVEE1, needs to extend all the way to the side of the first light-emitting device 41 close to the first edge 1. At this time, if the electrostatic protection circuit 91 is also arranged on the upper frame of the side of the first pixel row 31 close to the first edge 1, the second negative power signal line PVEE2 and the connection line between the first protection transistor M1 and the first fixed potential signal line VGH, and the connection line between the second protection transistor M2 and the second fixed potential signal line VGL may overlap in wiring position, or the first negative power signal line PVEE1 and the gates of the first protection transistor M1 and the second protection transistor M2 may overlap in wiring position.

[0094] In the embodiment of the present invention, by setting the positive electrode 411 of the first light-emitting device 41 on the side of the negative electrode 412 of the first light-emitting device 41 close to the first pixel circuit 42, the setting position of the first negative power signal line PVEE1 can be adjusted accordingly, so that it overlaps with the negative electrode 412 of the first light-emitting device 41 or is located on the side of the first light-emitting device 41 close to the first pixel circuit 42. At this time, the second negative power signal line PVEE2 does not need to extend to the side of the first light-emitting device 41 close to the first edge 1. At the same time, by moving the electrostatic protection circuit 91 from the upper frame to between two adjacent first light-emitting devices 41 in the second pixel row 31, the positions of the negative power signal line and the electrostatic protection circuit 91 can be optimized at the same time, avoiding the short circuit between the negative power signal line and the electrostatic protection circuit 91, or the overlapping of the wiring position of the negative power signal line and the connection line of the electrostatic protection circuit 91, optimizing the layout design, and avoiding short circuits between the wiring lines, thereby improving the electrostatic protection capability of the display panel.

[0095] In an optional embodiment, see again Figure 4 The first pixel circuit 42 and the second pixel circuit 52 in the second pixel row 321 are arranged in a mirror-symmetrical manner in the first direction x.

[0096] When designing the layout of the pixel circuit, the ninth transistor T9 in the pixel circuit for electrically connecting to the positive electrode of the light-emitting device is usually arranged on a side close to the positive electrode of the light-emitting device, so that the connection distance between the ninth transistor T9 and the positive electrode can be reduced. That is, it can be understood that if the positive electrode of the light-emitting device is located at the lower side of the pixel circuit, the ninth transistor T9 in the pixel circuit is located at the lower position of the entire pixel circuit.

[0097] As mentioned above, in the embodiment of the present invention, after the setting position of the first pixel circuit 42 is adjusted, since the positive and negative electrodes in the first light-emitting device 41 are still in the same direction as the positive and negative electrodes in the second light-emitting device 51, the positive electrode 411 of the first light-emitting device 41 is located on the side of the negative electrode 412 away from the first pixel circuit 42, so as to avoid adjusting the direction of the light-emitting device grown in the growth substrate, or reversing the light-emitting device when binding. Therefore, in the embodiment of the present invention, by making the first pixel circuit 42 and the second pixel circuit 52 in the second pixel row 321 mirror-symmetrically arranged, it is equivalent to flipping the first pixel circuit 42 based on the first light-emitting device 41, so that the connection distance between the ninth transistor T9 in the first pixel circuit 42 and the positive electrode 411 in the first light-emitting device 41 can be reduced, not only when the first pixel circuit 42 transmits the driving current to the first light-emitting device 41, but also the signal attenuation can be reduced, and the accuracy of the light-emitting brightness of the first light-emitting device 41 can be improved, and the space occupied by the connection wiring between the first pixel circuit 42 and the first light-emitting device 41 can be saved.

[0098] In one possible implementation, see again Figure 3 , the distance between the edge of the first light emitting device 41 and the edge of the second light emitting device 51 in the second pixel row 321 is d1, and the distance between the edges of the second light emitting devices 51 in two adjacent second pixel rows 32 is d2, d1=d2. It should be noted that in the process of the display panel, considering the factor of process error, the equality of d1 and d2 can specifically refer to the equality of d1 and d2 within the range of ±50μm, that is, when |d1-d2|≤50μm, d1 and d2 can be regarded as equal.

[0099] This setting method can be regarded as not changing the position of the first light-emitting device 41. At this time, the spacing between the first light-emitting device 41 and the second light-emitting device 51 in the second A pixel row 321 is still equal to the spacing between the second light-emitting devices 51 in any other two adjacent second pixel rows 32. The light-emitting devices in different pixel rows 3 in the display panel 100 are distributed at equal intervals, and the display uniformity of the display panel 100 is better.

[0100] In a possible implementation, Fig.15 As shown, Fig.15A schematic diagram of the setting position of the shift register 20 provided in an embodiment of the present invention, the display panel 100 also includes a plurality of shift registers 20 arranged in cascade, and the shift registers 20 are located in at least part of the first spacing area 7. Exemplarily, the display panel 100 may include a multi-stage first shift register electrically connected to a plurality of first scanning signal lines Scan1, a multi-stage second shift register electrically connected to a plurality of second scanning signal lines Scan2, and a multi-stage third shift register electrically connected to a plurality of light-emitting control signal lines Emit. Among them, the plurality of shift registers 20 arranged in cascade are used to sequentially output enable levels, and the signal lines electrically connected thereto transmit the enable levels to the first pixel circuit 42 or the second pixel circuit 52, so as to control the first pixel circuit 42 or the second pixel circuit 52 to work normally.

[0101] The first spacing area 7 set between two adjacent pixel rows 3 in the embodiment of the present invention can be used to accommodate the shift register 20. In other words, the reason why the first spacing area 7 is set between two adjacent pixel rows 3 in the embodiment of the present invention is to reserve a setting space for the shift register 20 in the display area, so that the shift register 20 can be set between part of the second pixel rows 32, thereby realizing that the shift register 20 is set in the display area of ​​the display panel 100, so that the shift register 20 does not need to occupy the left and right frame space, not only can the left and right ultra-narrow frame design or the left and right borderless design of the display panel 100 be better realized, but also when the display panel 100 is used in a spliced ​​display device, for two display panels 100 adjacent to each other in the second direction y, the spacing between adjacent light-emitting devices in the two display panels 100 can be reduced, thereby weakening the visual seams extending in the first direction x.

[0102] In one possible implementation, see again Figure 4 The positive electrode 511 of the second light-emitting device 51 is electrically connected to the second pixel circuit 52, and the negative electrode 512 of the second light-emitting device 51 is electrically connected to the third negative power signal line PVEE3, and the third negative power signal line PVEE3 is located in the first spacing area 7 on the side of the second light-emitting device 51 away from the first pixel row 31.

[0103] In the embodiment of the present invention, the first spacing area 7 provided between two adjacent pixel rows 3 can also be used to accommodate the third negative power signal line PVEE3. Moreover, as mentioned above, the cathode 512 of the second light emitting device 51 is located on the side of the anode 511 away from the first pixel row 31. By providing the third negative power signal line PVEE3 in the first spacing area 7 on the side of the second pixel row 32 away from the first pixel row 31 where the second light emitting device 51 electrically connected thereto is located, the third negative power signal line PVEE3 can also be closer to the cathode 512 of the second light emitting device 51, so that the connection distance is shorter, thereby facilitating the electrical connection between the two.

[0104] In a possible implementation, combining Figure 4 , Fig.12 and Fig.16 , Fig.16 for Fig.12 In a cross-sectional view along the A1-A2 direction, the positive electrode 411 of the first light-emitting device 41 is electrically connected to the first pixel circuit 42, the negative electrode 412 of the first light-emitting device 41 is electrically connected to the first negative power signal line PVEE1, and the first negative power signal line PVEE1 extends along the second direction y. In a direction perpendicular to the plane where the display panel 100 is located, the first negative power signal line PVEE1 overlaps with the first light-emitting device 41, specifically, the first negative power signal line PVEE1 can overlap with the negative electrode 412 of the first light-emitting device 41.

[0105] See also Figure 4 The second light-emitting device 51 is electrically connected to the third negative power signal line PVEE3, and the third negative power signal line PVEE3 is located on one side of the second light-emitting device 51. The second light-emitting device 51 needs to be connected to the third negative power signal line PVEE3 through a connecting line 80 extending along the first direction x. At this time, the connecting line 80 and the third negative power signal line PVEE3 both need to occupy additional space in the first direction x.

[0106] As for the first light-emitting device 41, the embodiment of the present invention sets the first negative power signal line PVEE1 to overlap with the first light-emitting device 41, so that the negative electrode 412 of the first light-emitting device 41 can be directly electrically connected to the first negative power signal line PVEE1 through the second connecting portion 50 located on one side of the negative electrode 412, and no additional connecting line is required between the second connecting portion 50 and the first negative power signal line PVEE1, thereby saving the space occupied by the connecting line and the first negative power signal line PVEE1 in the first direction x. In particular, the line width of the power signal line in the display panel 100 is much larger than the line width of other signal lines, so that more setting space can be vacated for the first pixel circuit 42 in the first spacing area 7 corresponding to the second A pixel row 321, so that the first pixel circuit 42 can be properly accommodated between the first light-emitting device 41 and the second light-emitting device 51 of the second A pixel row 321.

[0107] In addition, it should be noted that see Fig.16The display panel 100 includes a substrate 60, a buffer layer 61 located on one side of the substrate 60, a gate insulating layer 62 located on the side of the buffer layer facing away from the substrate 60, an interlayer insulating layer 63 located on the side of the gate insulating layer 62 facing away from the substrate 60, and a planarization layer 64 located on the side of the interlayer insulating layer 63 facing away from the substrate 60. The first negative power signal line PVEE1 may be located between the buffer layer 61 and the gate insulating layer 62, and the second connection portion 50 may be electrically connected to the first negative power signal line PVEE1 through a first auxiliary connection portion 65 located between the planarization layer 64 and the interlayer insulating layer 63 and a second auxiliary connection portion 66 located between the interlayer insulating layer 63 and the gate insulating layer 62, so as to improve the connection reliability between the two.

[0108] Furthermore, if Fig.17 As shown, Fig.17 Another top view of the display panel 100 provided in an embodiment of the present invention, the display panel 100 also includes a plurality of shift registers 20 arranged in cascade, the shift register 20 is located in at least part of the first spacing area 7; the size of the first pixel circuit 42 in the first direction x is r1, the size of the shift register 20 in the first direction x is r2, r1<r2, and part of the first light-emitting device 41 is located in the first spacing area 7 corresponding to the second A pixel row 321.

[0109] The dimension r1 of the first pixel circuit 42 in the first direction x is smaller than the dimension r2 of the shift register 20 in the first direction x. Therefore, the longitudinal width required to be occupied by the first pixel circuit 42 in the first spacing area 7 is smaller. At this time, the position of the first light-emitting device 41 can be further adjusted: the first light-emitting device 41 is moved along the direction of the second light-emitting device 51, so that part of the first light-emitting device 41 is located in the first spacing area 7 corresponding to the second A pixel row 321, that is, the distance between the first light-emitting device 41 and the second light-emitting device 51 in the second A pixel row 321 is reduced to release a larger cutting width on the upper border.

[0110] Moreover, since this arrangement can reduce the upper frame to a narrower size, the width of the lower frame of the display panel 100 can be compensated for to a greater extent without increasing the design size of the display panel 100. This arrangement is more suitable for display panels 100 that have a larger demand for the width of the lower frame. For example, if the number of pins 6 in the display panel 100 is large, the pins 6 need to occupy a large space at the lower frame. Although the above arrangement will slightly change the spacing between the first light-emitting device 41 and the second light-emitting device 51 adjacent thereto, it can release a larger cutting width for the upper frame to compensate for the width of the lower frame, and the lower frame can have sufficient pin setting space while improving the visual seam.

[0111] In one possible implementation, see again Fig.15 The display panel 100 further includes a plurality of shift registers 20 arranged in cascade connection, and the shift register 20 is located in at least a portion of the first spacing region 7 on a side of the second pixel row 321 away from the first pixel row 31 .

[0112] In an embodiment of the present invention, the first spacing area 7 set between two adjacent pixel rows 3 can be used to accommodate the shift register 20, so that the shift register 20 is set in the display area of ​​the display panel 100, avoiding the shift register 20 from occupying the left and right frame space, which can not only better realize the left and right ultra-narrow frame design or the left and right frameless design of the display panel 100, but also when the display panel 100 is used in a spliced ​​display device, for two adjacent display panels 100 in the second direction y, it can also reduce the spacing between adjacent light-emitting devices in the two display panels 100, thereby weakening the visual seams extending in the first direction x.

[0113] Moreover, the embodiment of the present invention can prevent the shift register 20 and the first pixel circuit 42 from occupying the space of the same first spacing area 7 by setting the shift register 20 in the first spacing area 7 on the side of the second pixel row 321 away from the first pixel row 31, so that each of them can have a sufficient setting position, which can not only optimize the layout design of the first pixel circuit 42 and the shift register 20, but also prevent the first light-emitting device 41 in the first pixel row 31 and the second light-emitting device 51 in the second pixel row 321 from being too far apart, which is conducive to achieving the overall uniform arrangement of the light-emitting devices and effectively improving the display uniformity. Moreover, this setting method can also realize the reasonable use of the first spacing area 7, and better combine it with the solution of narrowing the upper frame by adjusting the position of the first pixel circuit 42.

[0114] Further, see again Fig.15 , the second pixel row 32 also includes a second B pixel row 322 adjacent to the second A pixel row 321. The shift register 20 includes a first-stage shift register 201 electrically connected to the first pixel row 31 and a second-stage shift register 202 electrically connected to the second A pixel row 321. The first-stage shift register 201 and the second-stage shift register 202 are located in the first spacing area 7 corresponding to the second B pixel row 322, that is, in the first spacing area 7 between the second A pixel row 321 and the second B pixel row 322.

[0115] When the shift register 20 is set in the first spacing area 7, in order to reduce the distance between the corresponding shift registers 20 and the pixel rows 3, the shift register 20 can be set in the first spacing area 7 close to the pixel rows 3. As for the first-stage shift register 201 electrically connected to the first pixel row 31 and the second-stage shift register 202 electrically connected to the second A pixel row 321, by setting them in the first spacing area 7 corresponding to the second B pixel row 322, it can be avoided that the two-stage shift register 20 squeezes the setting space of the first pixel circuit 42, and it can also be avoided that the two-stage shift register 20 and the pixel rows 3 electrically connected thereto are too far apart, thereby reducing the voltage drop of the signal during transmission.

[0116] In one possible implementation, see again Fig.15 The display panel 100 further includes a plurality of shift registers 20 arranged in cascade. The second pixel row 32 further includes a second C pixel row 323 adjacent to the second edge 2, and the shift register 20 is located in at least part of the first spacing area 7 on the side of the second C pixel row 323 away from the second edge 2.

[0117] In the above-mentioned setting method, the shift register 20 will not occupy the outer side (the side close to the second edge 2) space of the second C pixel row 323. In one setting method, the setting space originally reserved for the shift register 20 of the lower frame can be cut off to reduce the width of the lower frame, thereby weakening the visual seam. Alternatively, in another setting method, the setting space originally reserved for the shift register 20 of the lower frame can be used to accommodate pin 6, optimize the arrangement of pin 6, and further reduce signal interference.

[0118] In addition, it should be noted that when the shift register 20 is located on the side of the second pixel row 321 away from the first pixel row 31 and on the side of the second pixel row 323 away from the second edge 2, two shift registers 20 can be set in part of the first spacing area 7.

[0119] In a possible implementation, Fig.18 and Fig.19 As shown, Fig.18 A schematic diagram of a setting position of the gating circuit 30 provided in an embodiment of the present invention, Fig.19 Schematic diagram of a structure of a gating circuit 30 provided in an embodiment of the present invention, the display panel 100 further includes a gating circuit 30, and the gating circuit 30 is electrically connected to the first sub-pixel 4 and the second sub-pixel 5 through the data line Data. The second pixel row 32 further includes a second C pixel row 323 adjacent to the second edge 2, and the gating circuit 30 is located in at least a portion of the first spacing region 7 on a side of the second C pixel row 323 away from the second edge 2.

[0120] In one configuration, see Fig.19 The gating circuit 30 includes a plurality of gating switches 301. The plurality of gating switches 301 in one gating circuit 30 are electrically connected to the same source signal line S. The plurality of gating switches 301 in one gating circuit 30 are electrically connected to a plurality of data lines respectively. By controlling the gating switches 301 in the gating circuit 30 to be turned on in time division, the data voltage provided by the source signal line S can be written into different data lines in time division. Setting the gating circuit 30 can reduce the number of pins 6 required to be set in the lower frame, thereby reducing the space required for the pins 6 to be occupied at the lower frame.

[0121] In the related art, the enabling circuit 30 is usually located in the lower frame of the display panel 100. In the embodiment of the present invention, by setting the enabling circuit 30 in the first spacing area 7, the enabling circuit 30 no longer occupies the outer side (the side close to the second edge 2) of the second C pixel row 323. In one setting method, the setting space originally reserved for the enabling circuit 30 in the lower frame can be cut off to reduce the width of the lower frame and thus weaken the visual seam. Alternatively, in another setting method, the setting space originally reserved for the enabling circuit 30 in the lower frame can be used to accommodate the pin 6, optimize the arrangement of the pin 6, and further reduce signal interference.

[0122] Further, see Fig.18 , the selection circuit 30 can be set in the first spacing area 7 corresponding to the second C pixel row 323. At this time, the selection circuit 30 is close to the pin 6, which can reduce the extension length of the source signal line S electrically connected between the selection circuit 30 and the pin 6 and reduce the voltage drop of the data voltage.

[0123] Moreover, in the embodiments of the present invention, see Fig.18 The shift register 20 can also be set in the first spacing area 7 on the side of the second pixel row 32 adjacent to the second pixel row 323 away from the second pixel row 323, so as to avoid the shift register 20 and the gating circuit 30 occupying the space of the same first spacing area 7, so that each of them can have enough setting position, which can not only optimize the layout design of the gating circuit 30 and the shift register 20, but also avoid the last two second pixel rows 32 being too far apart, which is conducive to the overall uniform arrangement of the light-emitting devices in the display panel 100.

[0124] In a possible implementation, Fig. 20 and Fig.21 As shown, Fig. 20 This is another top view of the display panel 100 provided by the embodiment of the present invention. Fig.21Another top view of the spliced ​​display device provided by an embodiment of the present invention, the distance between the first edge 1 and the edge of the first light-emitting device 41 is L1, and the distance between the second edge 2 and the edge of the second light-emitting device 51 closest thereto is L2. The distance between the edges of the second light-emitting devices 51 in two adjacent second pixel rows 32 is L, and L1+L2≤L.

[0125] In one arrangement, L1+L2=L.

[0126] Under this structure, for two display panels 100 adjacent to each other along the first direction x in the spliced ​​display device, the interval between the second light-emitting device 51 of the second pixel row 323 in the previous display panel 100 and the first light-emitting device 41 of the first pixel row 31 in the subsequent display panel 100 is equal to the distance between the second light-emitting devices 51 in two adjacent second pixel rows 32 in the same display panel 100. At this time, the arrangement of the light-emitting devices of the spliced ​​display device as a whole is more uniform, and the spliced ​​display device achieves seamless splicing, thereby eliminating visual seams.

[0127] Alternatively, in another configuration, L1+L2<L.

[0128] When L1+L2 is not equal to L, the reason why the embodiment of the present invention sets L1+L2 to be less than L, rather than greater than L, is that: on the one hand, in some cases, when the display panels 100 are spliced ​​to form a spliced ​​display device, a glue layer can be set between the display panels 100 to bond and fix the display panels 100, thereby improving the splicing reliability. Moreover, the glue layer can also avoid optical problems such as refraction caused by the presence of air in the panel gap. Therefore, by setting L1+L2 to be less than L, a margin can be reserved for the design size and process accuracy of the glue layer. Even if there are some errors in the frame width or the glue layer width due to the setting of the glue layer and factors such as process accuracy, the interval between the second light-emitting device 51 of the second pixel row 323 in the previous display panel 100 and the first light-emitting device 41 of the first pixel row 31 in the next display panel 100 will not differ too much from L. On the other hand, the interval (interval width is L1+L2) between the second light-emitting device 51 of the second pixel row 323 in the previous display panel 100 and the first light-emitting device 41 of the first pixel row 31 in the next display panel 100 is a non-luminous area. The wider the interval, the easier it is for the non-luminous area to be visible to the human eye. Therefore, the embodiment of the present invention chooses to set L1+L2 to be less than L, which can make the above-mentioned interval width smaller, thereby reducing the risk of the joint seam of the display panel 100 being visible to the human eye.

[0129] In a possible implementation, Fig. 22 As shown, Fig. 22Another top view of the display panel 100 provided by the embodiment of the present invention, the second pixel row 32 includes a second C pixel row 323 adjacent to the second edge 2, the second C pixel row 323 includes a plurality of pixel units 40 arranged along the second direction y, the pixel unit 40 includes a plurality of second sub-pixels 5 arranged along the second direction y, and illustratively, the pixel unit 40 includes a second sub-pixel 5 for emitting red light, a second sub-pixel 5 for emitting green light, and a second sub-pixel 5 for emitting blue light. The distance between two adjacent pixel units 40 may be greater than the distance between two adjacent second sub-pixels 5 in the pixel unit 40.

[0130] A second spacing area 70 is included between two adjacent pixel units 40 in the second C pixel row 323 . The display panel 100 further includes a pin 6 . The pin 6 is located on a side close to the second edge 2 . In the first direction x, the pin 6 overlaps with the second spacing area 70 .

[0131] If the pin 6 is set directly below the pixel unit 40, the pin 6 overlaps with the pixel unit 40 in the first direction x. When the trace is led out from the pin 6 along the first direction x, in order to avoid a short circuit between this part of the trace and the trace led out from the second light-emitting device 51, the pin 6 needs to be spaced a certain distance from the pixel unit 40, which results in a greater demand for the width of the bottom frame of the display panel 100. In the above arrangement, by setting the pin 6 below the second spacing area 70, the risk of a short circuit between the trace electrically connected to the pin 6 and the electrode of the second light-emitting device 51 can be reduced. At this time, the pin 6 can be moved slightly in the direction toward the first edge 1, thereby reducing the design demand for the width of the bottom frame, and then the width of the bottom frame of the display panel 100 can be narrowed or a smaller compensation can be made for the width of the bottom frame.

[0132] Furthermore, if Fig.23 As shown, Fig.23 This is another top view of the display panel 100 provided by the embodiment of the present invention. At least a portion of the pin 6 may be located in the second spacing area 70 .

[0133] When at least part of the pin 6 is located in the second spacing area 70, at least part of the pin 6 is equivalent to being set in the display area, and the lower frame can be narrowed to a greater extent. Moreover, in this arrangement, the data line Data or the source signal line S can be directly connected to the pin 6 in the display area, thereby eliminating the fan-out wiring in the lower frame, further saving the space required for the fan-out wiring in the lower frame, and further narrowing the lower frame. When the display panel 100 is used in a spliced ​​display device, the visual seam can be better eliminated.

[0134] Based on the same inventive concept, an embodiment of the present invention further provides a splicing display device, such as Fig.24As shown, Fig.24 A schematic diagram of a structure of a spliced ​​display device provided in an embodiment of the present invention, the spliced ​​display device comprises n display panels 100, wherein at least two display panels 100 are spliced ​​along a first direction x, and n≥2. The specific structure of the display panel 100 has been described in detail in the above embodiment, and will not be repeated here. Of course, Fig.24 The spliced ​​display device shown is only for illustrative purposes. The spliced ​​display device may be, for example, an LED spliced ​​screen, a movie screen, a long-distance viewing electronic product, etc.

[0135] Furthermore, if Fig.25 As shown, Fig.25 Another structural schematic diagram of a spliced ​​display device provided by an embodiment of the present invention, the spliced ​​display device further includes a first adhesive layer 200, the first adhesive layer 200 is located between two adjacent display panels 100 in the first direction x, and the width of the first adhesive layer 200 in the first direction x is k. In the display panel 100, the distance between the first edge 1 and the edge of the first light-emitting device 41 is L1, the distance between the second edge 2 and the edge of the second light-emitting device 51 closest thereto is L2, and the distance between the edges of the second light-emitting devices 51 in two adjacent second pixel rows 32 is L, and L1+L2+k≤L.

[0136] By setting the first adhesive layer 200 between the display panels 100, the display panels 100 can be bonded by the first adhesive layer 200, thereby improving the splicing reliability of the spliced ​​display device. Moreover, the first adhesive layer 200 can also prevent the presence of air in the gaps between the display panels 100, thereby preventing optical problems such as refraction. In the embodiment of the present invention, by setting L1+L2+k to be less than or equal to L, a certain margin can be reserved for process errors, so that the interval between the second light-emitting device 51 of the last second pixel row 32 in the previous display panel 100 and the first light-emitting device 41 of the first pixel row 31 in the next display panel 100 will not differ too much from L, so that the spliced ​​display device can eliminate visual seams as much as possible and better achieve seamless splicing.

[0137] Furthermore, since the width of the adhesive layer is usually about 100 μm, L1+L2 can satisfy: L1+L2+100 μm≤L.

[0138] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: a first edge and a second edge disposed opposite to each other in a first direction; A plurality of pixel rows arranged along the first direction, the pixel rows comprising a first pixel row and a plurality of second pixel rows, wherein the first pixel row is adjacent to the first edge, the first pixel row comprises a plurality of first sub-pixels arranged along the second direction, the first sub-pixels comprise electrically connected first light-emitting devices and first pixel circuits, the second pixel row comprises a plurality of second sub-pixels arranged along the second direction, the second sub-pixels comprise electrically connected second light-emitting devices and second pixel circuits, and the first direction intersects the second direction; a plurality of first spacing regions corresponding to the plurality of second pixel rows one by one, wherein the first spacing regions are located on a side of the corresponding second pixel row close to the first edge, and the first spacing regions are adjacent to the corresponding second pixel row; The second pixel row includes a second A pixel row adjacent to the first pixel row, the first pixel circuit is located on a side of the first light-emitting device away from the first edge, and the first pixel circuit is located in the first spacing area corresponding to the second A pixel row, and the second pixel circuit is located on a side of the second light-emitting device close to the first edge; The positive electrode of the first light-emitting device is electrically connected to the first pixel circuit through the first connecting portion, the negative electrode of the first light-emitting device is electrically connected to the first negative power signal line, and the positive electrode of the first light-emitting device is located on a side of the negative electrode of the first light-emitting device away from the first pixel circuit; The first negative power signal line extends along the second direction, the first negative power signal line is also electrically connected to a plurality of second negative power signal lines, and the second negative power signal lines extend along the first direction; The display panel further includes an electrostatic protection circuit, the electrostatic protection circuit is located between two adjacent first light-emitting devices in the first pixel row, and the electrostatic protection circuit is located on a side of the first negative power signal line away from the first pixel circuit; The electrostatic protection circuit includes a first protection transistor and a second protection transistor, the first protection transistor is electrically connected to a first fixed potential signal line, the second protection transistor is electrically connected to a second fixed potential signal line, and the first fixed potential signal line and the second fixed potential signal line are located on a side of the first pixel row away from the second pixel row.

2. The display panel according to claim 1, characterized in that: The distance between the first edge and the edge of the first light emitting device is L1, the distance between the second edge and the edge of the second light emitting device closest thereto is L2, and L2>L1.

3. The display panel according to claim 1, characterized in that: The display panel also includes a pin, which is located on a side close to the second edge and electrically connected to one end of a side trace. The side trace is bent to the backlight side of the display panel, and the other end of the side trace is used to be electrically connected to a circuit board.

4. The display panel according to claim 1, characterized in that: The display panel also includes a first driving signal line electrically connected to the first pixel circuit, the first driving signal line extends along the second direction, and the first driving signal line is located in the first spacing area corresponding to the second A pixel row.

5. The display panel according to claim 4, characterized in that: The first pixel circuit is electrically connected to the scanning signal line, the first positive power signal line, the reset signal line and the light emitting control signal line respectively; The first driving signal line includes at least one of the scanning signal line, the first positive power signal line, the reset signal line, and the light emission control signal line.

6. The display panel according to claim 1, characterized in that: A first connecting wire is connected between the first connecting portion and the first pixel circuit, the first connecting wire includes a first wire segment and a second wire segment that are connected, an end of the first wire segment is electrically connected to the first connecting portion, at least a portion of the first wire segment extends along the second direction, and the second wire segment extends on one side of the first light-emitting device in the second direction.

7. The display panel according to claim 6, characterized in that: The first wiring segment extends along the second direction, and the first connecting portion is located on one side of the anode of the first light-emitting device in the second direction.

8. The display panel according to claim 1, characterized in that: The first pixel circuit and the second pixel circuit in the second A pixel row are arranged in a mirror-symmetrical manner in the first direction.

9. The display panel according to claim 1, characterized in that: The distance between the edge of the first light emitting device and the edge of the second light emitting device in the second A pixel row is d1, and the distance between the edges of the second light emitting devices in two adjacent second pixel rows is d2, d1=d2.

10. The display panel according to claim 9, characterized in that: The display panel further includes a plurality of shift registers arranged in cascade connection, and the shift registers are located in at least a portion of the first spacing area.

11. The display panel according to claim 9, characterized in that: The anode of the second light emitting device is electrically connected to the second pixel circuit, and the cathode of the second light emitting device is electrically connected to a third negative power signal line, which is located in the first spacing area on the side of the second light emitting device away from the first pixel row.

12. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the display panel is located, the first negative power signal line overlaps with the first light emitting device.

13. The display panel according to claim 12, characterized in that: The display panel further comprises a plurality of shift registers arranged in cascade, wherein the shift registers are located in at least a portion of the first spacing area; The size of the first pixel circuit in the first direction is r1, the size of the shift register in the first direction is r2, r1<r2, and part of the first light-emitting device is located in the first spacing area corresponding to the second A pixel row.

14. The display panel according to claim 1, characterized in that: The display panel also includes a plurality of shift registers arranged in cascade; The shift register is located in at least a portion of the first spacing area on a side of the second A pixel row away from the first pixel row.

15. The display panel according to claim 14, characterized in that: The second pixel row further includes a second B pixel row adjacent to the second A pixel row; The shift register includes a first-stage shift register electrically connected to the first pixel row and a second-stage shift register electrically connected to the second A pixel row. The first-stage shift register and the second-stage shift register are respectively located in the first spacing area corresponding to the second B pixel row.

16. The display panel according to claim 1, characterized in that: The display panel also includes a plurality of shift registers arranged in cascade; The second pixel row further includes a second C pixel row adjacent to the second edge, and the shift register is located in at least a portion of the first spacing area on a side of the second C pixel row away from the second edge.

17. The display panel according to claim 1, characterized in that: The display panel further includes a gating circuit, wherein the gating circuit is electrically connected to the first sub-pixel and the second sub-pixel through a data line; The second pixel row further includes a second C pixel row adjacent to the second edge, and the gating circuit is located in at least a portion of the first spacing region on a side of the second C pixel row away from the second edge.

18. The display panel according to claim 1, characterized in that: The distance between the first edge and the edge of the first light-emitting device is L1, and the distance between the second edge and the edge of the second light-emitting device closest thereto is L2; The distance between the edges of the second light emitting devices in two adjacent second pixel rows is L, and L1+L2≤L.

19. The display panel according to claim 1, characterized in that: The second pixel row includes a second C pixel row adjacent to the second edge, the second C pixel row includes a plurality of pixel units arranged along the second direction, and the pixel unit includes a plurality of the second sub-pixels arranged along the second direction; A second spacing area is included between two adjacent pixel units in the second C pixel row; The display panel further includes a pin, wherein the pin is located at a side close to the second edge, and the pin overlaps the second spacer in the first direction.

20. The display panel according to claim 19, characterized in that: At least a portion of the pin is located in the second spacing area.

21. A splicing display device, characterized in that: The method comprises n display panels according to any one of claims 1 to 20, wherein at least two of the display panels are spliced ​​along the first direction, and n≥2.

22. The splicing display device according to claim 21, characterized in that: The spliced ​​display device further includes a first adhesive layer, the first adhesive layer is located between two adjacent display panels in the first direction, and the width of the first adhesive layer in the first direction is k; In the display panel, the distance between the first edge and the edge of the first light-emitting device is L1, the distance between the second edge and the edge of the second light-emitting device closest thereto is L2, and the distance between the edges of the second light-emitting devices in two adjacent second pixel rows is L, L1+L2+k≤L.

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