Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a memory system. The semiconductor device comprises a plurality of silicon columns arranged in an array; the oxidation insulating layer is arranged between any two adjacent silicon columns; the bit lines are arranged on one side of the silicon column; according to the semiconductor device provided by the invention, an isolation structure used for reducing coupling capacitance can be formed on the oxidation insulating layer between two adjacent bit lines, and the first insulating layer is arranged on the side, deviating from the silicon column, of the bit lines, so that the isolation structure can be used for reducing the coupling capacitance, and the isolation structure can be used for reducing the coupling capacitance. According to the semiconductor device, the gap between the first insulating layers arranged on the sides, away from the silicon column, of the two adjacent bit lines can be further utilized, so that the arrangement space of the isolation structure is increased, the coupling capacitance between the bit lines is reduced, the sensing tolerance of the semiconductor device is improved, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a method for manufacturing the same, and a memory system. Background Art

[0002] In the electronics industry, three-dimensional (3D) stacking technology facilitates the integration of semiconductor devices. To form a 3D stack, two or more chips are arranged one on top of the other and bonded.

[0003] In a three-dimensional dynamic random access memory (3D DRAM), there is a coupling capacitance between two adjacent bit lines (Bit Line). When the coupling capacitance between the bit lines is too large, the sensing tolerance of the 3D DRAM will be reduced and the device performance will be degraded.

[0004] Therefore, how to reduce the coupling capacitance between bit lines, increase the sensing tolerance of 3D DRAM, and improve device performance is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] The present application provides a semiconductor device and a method for manufacturing the same, and a memory system, which can effectively solve the problem of large coupling capacitance between bit lines in a semiconductor device.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a plurality of silicon pillars arranged in an array; an oxide insulating layer arranged between any two adjacent silicon pillars; a plurality of bit lines, the bit lines being arranged on one side of the silicon pillars; and a first insulating layer, the first insulating layer being arranged on a side of the bit lines away from the silicon pillars.

[0007] In some embodiments, the semiconductor device further includes a hollow dielectric layer, which is disposed on a side of the first insulating layer away from the silicon pillars and fills gaps between the silicon pillars, gaps between the bit lines, and gaps between the first insulating layers.

[0008] In some embodiments, the hollow dielectric layer includes a plurality of air gaps, and at least one of the air gaps is disposed between any two adjacent bit lines.

[0009] In some embodiments, the bit line includes a first film layer and a second film layer stacked in sequence on one side of the silicon pillar, wherein a groove is provided on the side of the second film layer facing away from the first film layer, and the groove is filled with a third film layer; and the first insulating layer is provided on the surface of the second film layer and the third film layer facing away from the first film layer.

[0010] In some embodiments, the first film layer includes a silicon-metal compound, the second film layer includes a titanium nitride compound, and the material of the third film layer includes tungsten.

[0011] In some embodiments, the bit line includes a first film layer, and the first insulating layer is disposed on a surface of the first film layer that is away from the oxidized insulating layer.

[0012] In some embodiments, the first insulating layer includes an oxide of the material of the first film layer.

[0013] In some embodiments, the first insulating layer includes a non-metal nitride.

[0014] In some embodiments, the material of the first insulating layer is the same as that of the oxidized insulating layer.

[0015] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising the following steps:

[0016] forming a plurality of silicon pillars arranged in an array, and forming an oxide insulating layer between the silicon pillars;

[0017] forming a bit line on one side of each of the silicon pillars;

[0018] forming a first insulating layer on a side of the bit line away from the silicon pillar;

[0019] A hollow dielectric layer is formed on a side of the first insulating layer away from the bit line.

[0020] In some embodiments, in the step of forming a plurality of silicon pillars arranged in an array and forming an oxidized insulating layer between the silicon pillars, the oxidized insulating layer and the silicon pillars form a plurality of first groove structures; in the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the first groove structure, and the oxidized insulating layer protrudes from the bit line; in the step of forming a first insulating layer on a side of the bit line away from the silicon pillar, a surface of the first insulating layer on a side away from the silicon pillar is flush with a surface of the oxidized insulating layer; before forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the following steps are also included: removing a portion of the oxidized insulating layer to expose at least a portion of the silicon pillar; in the step of forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0021] In some embodiments, in the step of forming a plurality of silicon pillars arranged in an array and forming an oxidized insulating layer between the silicon pillars, the oxidized insulating layer and the silicon pillars form a plurality of second groove structures; in the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the second groove structure; in the step of forming a first insulating layer on a side of the bit line away from the silicon pillar, the surface of the bit line is oxidized so that part of the bit line is transformed to form the first insulating layer; before forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the following steps are also included: removing part of the oxidized insulating layer to expose at least part of the silicon pillar; in the step of forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0022] In some embodiments, before the step of forming a bit line on one side of each silicon pillar, the step further includes: removing part of the oxidized insulating layer to expose at least part of the silicon pillar; forming a sacrificial layer on one side of the oxidized insulating layer, and the surface of the sacrificial layer is flush with the surface of the silicon pillar; removing part of the silicon pillar so that the sacrificial layer and the silicon pillar form a plurality of third groove structures; in the step of forming a bit line on one side of each silicon pillar, the bit line is formed in the third groove structure, and the sacrificial layer protrudes from the bit line; in the step of forming a first insulating layer on the side of the bit line away from the silicon pillar, the surface of the first insulating layer on the side away from the silicon pillar is flush with the surface of the sacrificial layer; before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the step further includes: removing the sacrificial layer to expose at least part of the silicon pillar; in the step of forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

[0023] In a third aspect, the present application provides a memory system, which includes a memory array structure and a peripheral structure connected to the memory array structure; at least one of the memory array structure and the peripheral structure includes any of the semiconductor devices described above.

[0024] The present application provides a semiconductor device and a preparation method thereof, and a memory system. The semiconductor device includes: a plurality of silicon pillars arranged in an array; an oxidized insulating layer arranged between any two adjacent silicon pillars; a plurality of bit lines, the bit lines being arranged on one side of the silicon pillars; and a first insulating layer, the first insulating layer being arranged on the side of the bit lines away from the silicon pillars. In the semiconductor device provided by the present application, an isolation structure for reducing coupling capacitance can be formed on the oxidized insulating layer between two adjacent bit lines, and since the first insulating layer is arranged on the side of the bit lines away from the silicon pillars, the gap between the first insulating layers arranged on the side of the two adjacent bit lines away from the silicon pillars can be further utilized to increase the setting space of the isolation structure, thereby reducing the coupling capacitance between the bit lines, improving the sensing tolerance of the semiconductor device, and enhancing the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1A schematic plan view of a semiconductor device provided for some embodiments of the present application.

[0027] Figure 2 Some embodiments of the present application provide Figure 1 A schematic cross-sectional view of a semiconductor device taken along line CC.

[0028] Figure 3 A schematic cross-sectional view of a semiconductor device corresponding to different steps provided in some embodiments of the present application.

[0029] Figure 4 Some embodiments of the present application provide Figure 1 A schematic cross-sectional view of another semiconductor device taken along line CC.

[0030] Figure 5 A schematic cross-sectional view of another semiconductor device corresponding to different steps provided in some embodiments of the present application.

[0031] Figure 6 Some embodiments of the present application provide Figure 1 A schematic cross-sectional view of another semiconductor device taken along line CC.

[0032] Figure 7 A schematic cross-sectional view of another semiconductor device corresponding to different steps provided in some embodiments of the present application.

[0033] Description of reference numerals:

[0034] Silicon pillar 10; oxidized insulating layer 20; first groove structure 21; bit line 30; first film layer 31; second film layer 32; third film layer 33; first insulating layer 40; hollow dielectric layer 50; air gap 51; closing portion 52; uniform opening portion 53;

[0035] Silicon pillar 10 ˋ; oxide insulating layer 20 ˋ; second groove structure 21 ˋ; bit line 30 ˋ; first film layer 31 ˋ; first insulating layer 40 ˋ; hollow dielectric layer 50 ˋ; air gap 51 ˋ; closing portion 52 ˋ; uniform opening portion 53 ˋ;

[0036] Silicon pillar 10ˋˋ; oxide insulating layer 20ˋˋ; bit line 30ˋˋ; first film layer 31ˋˋ; first insulating layer 40ˋˋ; hollow dielectric layer 50ˋˋ; air gap 51ˋˋ; closing portion 52ˋˋ; uniform opening portion 53ˋˋ; sacrificial layer 100; third groove structure 101; first direction X; second direction Y; third direction Z; DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0038] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0039] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0040] As used herein, the term "layer" refers to a material portion including an area with a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range that is smaller than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0041] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0042] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0043] Figure 1A schematic plan view of a semiconductor device provided in some embodiments of the present application; Figure 2 Some embodiments of the present application provide Figure 1 A schematic cross-sectional view of a semiconductor device cut along the CC line. Figure 1 and Figure 2 As shown, in the first aspect, an embodiment of the present application provides a semiconductor device, which includes: a plurality of silicon pillars 10 arranged in an array; an oxide insulating layer 20, arranged between any two adjacent silicon pillars 10; a plurality of bit lines 30, wherein the bit lines 30 are arranged on one side of the silicon pillars 10; and a first insulating layer 40, wherein the first insulating layer 40 is arranged on the side of the bit lines 30 away from the silicon pillars 10.

[0044] In some embodiments of the present application, a coupling capacitance effect is generated between two adjacent bit lines 30. By forming an isolation structure, such as an air gap 51, on the oxidized insulating layer 20 between the two adjacent bit lines 30, the dielectric constant of the coupling capacitance can be reduced, thereby improving the working efficiency of the semiconductor device. However, due to process limitations, a closing portion 52 is formed at one end of the air gap 51 away from the oxidized insulating layer 20, and the width of the closing portion 52 gradually narrows in the direction away from the oxidized insulating layer 20. When the closing portion 52 between the two adjacent bit lines 30 overlaps with the two adjacent bit lines 30 in the first direction X, the ability of the air gap 51 to improve the coupling capacitance is reduced, thereby causing the problem of a large coupling capacitance between the two adjacent bit lines 30.

[0045] In the semiconductor device provided in the present application, since the first insulating layer 40 is arranged on the side of the bit line 30 away from the silicon pillar 10, the setting position of the first insulating layer 40 corresponds to the setting position of the bit line 30. Therefore, a gap can be formed between the two first insulating layers 40 on two adjacent bit lines 30, and the gap is connected with the gap between the two adjacent bit lines 30, so that the setting space of the air gap 51 arranged on the oxide insulating layer 20 between the two adjacent bit lines 30 is increased, and then the position of the closing portion 52 is improved, so that the closing portion 52 can be formed above the gap between the two adjacent bit lines 30, thereby improving the ability of the air gap 51 to improve the coupling capacitance, improving the sensing tolerance of the semiconductor device, and enhancing the device performance.

[0046] In some embodiments of the present application, the bit line 30 extends along the second direction Y, the silicon pillar 10, the bit line 30 and the first insulating layer 40 are stacked in the third direction Z, and the setting of the first insulating layer 40 can change the position of the closing portion 52 in the third direction Z, so that the closing portion 52 does not overlap with the bit line 30 in the first direction X or the overlapping area is reduced.

[0047] In some embodiments of the present application, the semiconductor device also includes a hollow dielectric layer 50, which is arranged on the side of the first insulating layer 40 away from the silicon pillars 10 and fills the gaps between the silicon pillars 10, the gaps between the bit lines 30 and the gaps between the first insulating layers 40.

[0048] In the semiconductor device provided in the present application, the hollow dielectric layer 50 includes a plurality of hollow structures for forming the air gap 51 to reduce the dielectric constant of the coupling capacitor, thereby improving the working efficiency of the semiconductor device.

[0049] In some embodiments of the present application, the hollow dielectric layer 50 includes a plurality of air gaps 51 , and at least one air gap 51 is disposed between any two adjacent bit lines 30 .

[0050] Further, the air gap 51 includes a uniform opening portion 53 and a closing portion 52, wherein the closing portion 52 is arranged on a side of the uniform opening portion 53 away from the oxidized insulating layer 20, wherein in the direction away from the oxidized insulating layer 20, the uniform opening portion 53 has a uniform or quasi-uniform width, the width of the closing portion 52 gradually decreases, and the distance between the side of the uniform opening portion 53 away from the oxidized insulating layer 20 and the plane where the oxidized insulating layer 20 is located is greater than the distance between the bit line 30 and the plane where the oxidized insulating layer 20 is located, so that the uniform opening portion 53 can overlap with the bit line 30 in the first direction X, and the closing portion 52 does not overlap with the bit line 30 in the first direction X, thereby ensuring the effect of the air gap 51 on reducing the coupling capacitance between two adjacent bit lines 30, so that the coupling capacitance between two adjacent bit lines 30 is at a lower level, thereby improving the sensing tolerance of the semiconductor device and improving the device performance.

[0051] In some embodiments of the present application, the bit line 30 includes a first film layer 31 and a second film layer 32 stacked in sequence on one side of the silicon pillar 10, wherein a groove is provided on the side of the second film layer 32 away from the first film layer 31, and the third film layer 33 is filled in the groove; the first insulating layer 40 is provided on the surface of the second film layer 32 and the third film layer 33 away from the first film layer 31. Of course, the present application does not limit the film layer structure of the bit line 30. In other embodiments of the present application, the bit line 30 includes a first film layer, and the first insulating layer is provided on the surface of the first film layer away from the oxidized insulating layer.

[0052] In some embodiments of the present application, the first film layer 31 includes a silicon-metal compound, the second film layer 32 includes a titanium nitride compound, and the material of the third film layer 33 includes tungsten.

[0053] In some embodiments of the present application, the first insulating layer includes non-metal nitride.

[0054] Figure 3 A schematic cross-sectional view of a semiconductor device corresponding to different steps provided in some embodiments of the present application. Figure 1-Figure 3 As shown, in a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising the following steps:

[0055] Forming a plurality of silicon pillars 10 arranged in an array, and forming an oxide insulating layer 20 between the silicon pillars 10;

[0056] A bit line 30 is formed on one side of each of the silicon pillars 10;

[0057] Forming a first insulating layer 40 on a side of the bit line 30 away from the silicon pillar 10;

[0058] A hollow dielectric layer 50 is formed on a side of the first insulating layer 40 away from the bit line 30 .

[0059] In some embodiments of the present application, in the step of forming a plurality of silicon pillars 10 arranged in an array and forming an oxidized insulating layer 20 between the silicon pillars 10 , the oxidized insulating layer 20 and the silicon pillars 10 form a plurality of first groove structures 21 .

[0060] In some embodiments of the present application, in the step of forming the bit line 30 on one side of each of the silicon pillars 10 , the bit line 30 is formed in the first groove structure 21 , and the oxidized insulating layer 20 protrudes from the bit line 30 .

[0061] In some embodiments of the present application, in the step of forming the first insulating layer 40 on the side of the bit line 30 away from the silicon pillar 10 , the surface of the first insulating layer 40 away from the silicon pillar 10 is flush with the surface of the oxidized insulating layer 20 .

[0062] In some embodiments of the present application, before forming the hollow dielectric layer 50 on the side of the first insulating layer 40 away from the bit line 30, the following step is further included: removing part of the oxidized insulating layer 20 to expose at least part of the silicon pillar 10. Exemplarily, a chemical mechanical polishing (CMP) process may be used to remove part of the oxidized insulating layer 20.

[0063] In some embodiments of the present application, in the step of forming a hollow dielectric layer 50 on a side of the first insulating layer 40 away from the bit line 30, the hollow dielectric layer 50 fills the gaps between the silicon pillars 10, the gaps between the bit lines 30, and the gaps between the first insulating layers 40. The hollow dielectric layer 50 includes a plurality of air gaps 51, and at least one of the air gaps 51 is provided between any two adjacent bit lines 30.

[0064] It should be noted that due to the limitations of semiconductor technology, the surface of each film layer cannot be completely flat. Therefore, the situation in which the surface of a film layer is flush with the surface of another film layer described in the present application includes being completely flush or approximately flush. The approximately flush situation includes the height difference between the highest point of the surface of one film layer and the lowest point of the surface of another film layer being within a preset threshold range.

[0065] In a third aspect, an embodiment of the present application further provides a storage system, the storage system comprising a memory, the memory being the semiconductor device described in any one of the above or a part of the semiconductor device.

[0066] Figure 4 Some embodiments of the present application provide Figure 1 A schematic cross-sectional view of another semiconductor device cut along the CC line. Figure 1 and Figure 4 As shown, in the first aspect, an embodiment of the present application provides a semiconductor device, comprising: a plurality of silicon pillars 10' arranged in an array; an oxide insulating layer 20' arranged between any two adjacent silicon pillars 10'; a plurality of bit lines 30', wherein the bit lines 30' are arranged on one side of the silicon pillars 10'; and a first insulating layer 40', wherein the first insulating layer 40' is arranged on the side of the bit lines 30' away from the silicon pillars 10'.

[0067] It should be noted that if Figure 4 The semiconductor device shown is Figure 2 The structure of the semiconductor device shown is similar, for example, the semiconductor device also includes a hollow dielectric layer 50, which is arranged on the side of the first insulating layer 40 away from the silicon pillars 10, and fills the gaps between the silicon pillars 10, the gaps between the bit lines 30 and the gaps between the first insulating layers 40; the hollow dielectric layer 50 includes a plurality of air gaps 51, and at least one air gap 51 is arranged between any two adjacent bit lines 30, and the air gap 51 includes a closing portion 52 and a uniform opening portion 53, and the same parts are not repeated here.

[0068] The difference is that the bit line 30 includes a first film layer 31, and the first insulating layer 40 is disposed on a surface of the first film layer 31 facing away from the oxidized insulating layer 20. That is, the first film layer 31 is a film layer in the bit line 30 that contacts the first insulating layer 40.

[0069] In some embodiments of the present application, the bit line 30 ' only includes the first film layer 31 ', that is, the bit line 30 ' is a single film layer structure, so as to simplify the production and preparation process of the bit line 30 ' and improve the process efficiency.

[0070] In some embodiments of the present application, the bit line 30 ' includes a first film layer 31 ' and other film layers, and the other film layers are arranged between the first film layer 31 ' and the silicon pillar 10 ', that is, the first film layer 31 ' is the film layer in the bit line 30 ' that is farthest from the silicon pillar 10 '.

[0071] In some embodiments of the present application, the first insulating layer 40 includes an oxide of the material of the first film layer 31 .

[0072] Exemplarily, the first film layer 31 includes a silicon-metal compound, and the first insulating layer 40 includes an oxide of the silicon-metal compound.

[0073] In the semiconductor device provided in the present application, since the first insulating layer 40 ˋ includes the oxide of the first film layer 31 ˋ, that is, the first insulating layer 40 ˋ can be directly obtained through an oxidation process of the first film layer 31 ˋ, the preparation process is simple and the self-alignment effect of the first insulating layer 40 ˋ and the first film layer 31 ˋ can be achieved.

[0074] Figure 5 Another cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present application corresponding to different steps. Figure 1 , Figure 4 and Figure 5 As shown, in a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising the following steps:

[0075] A plurality of silicon pillars 10' are formed in an array, and an oxide insulating layer 20' is formed between the silicon pillars 10';

[0076] A bit line 30' is formed on one side of each of the silicon pillars 10';

[0077] Forming a first insulating layer 40' on a side of the bit line 30' away from the silicon pillar 10';

[0078] A hollow dielectric layer 50 ′ is formed on a side of the first insulating layer 40 ′ away from the bit line 30 ′.

[0079] In some embodiments of the present application, in the step of forming a plurality of silicon pillars 10 ′ arranged in an array and forming an oxidized insulating layer 20 ′ between the silicon pillars 10 ′, the oxidized insulating layer 20 ′ and the silicon pillars 10 ′ form a plurality of second groove structures 21 ′.

[0080] In some embodiments of the present application, in the step of forming a bit line 30' on one side of each silicon pillar 10', the bit line 30' is formed in the second groove structure 21'. Optionally, the surface of the oxide insulating layer 20' is flush with the surface of the bit line 30'.

[0081] In some embodiments of the present application, in the step of forming the first insulating layer 40' on the side of the bit line 30' away from the silicon pillar 10', the surface of the bit line 30' is oxidized so that part of the bit line 30' is transformed to form the first insulating layer 40'. Optionally, the surface of the first insulating layer 40' away from the silicon pillar 10' is flush with the surface of the oxidized insulating layer 20'.

[0082] In some embodiments of the present application, before forming the hollow dielectric layer 50 ′ on the side of the first insulating layer 40 ′ away from the bit line 30 ′, the following step is also included: removing part of the oxidized insulating layer 20 ′ to expose at least part of the silicon pillar 10 ′.

[0083] In some embodiments of the present application, in the step of forming a hollow dielectric layer 50 ′ on a side of the first insulating layer 40 ′ away from the bit line 30 ′, the hollow dielectric layer 50 ′ fills the gaps between the silicon pillars 10 ′, the gaps between the bit lines 30 ′, and the gaps between the first insulating layers 40 ′.

[0084] In the method for preparing a semiconductor device provided in an embodiment of the present application, since the surface of the bit line 30ˋ can be oxidized to transform part of the bit line 30ˋ into the first insulating layer 40ˋ, the first insulating layer 40ˋ can be directly obtained after an oxidation process of the first film layer 31ˋ. The preparation process is simple and a self-alignment effect of the first insulating layer 40ˋ and the first film layer 31ˋ can be achieved.

[0085] In a third aspect, an embodiment of the present application further provides a storage system, the storage system comprising a memory, the memory being the semiconductor device described in any one of the above or a part of the semiconductor device.

[0086] Figure 6 Some embodiments of the present application provide Figure 1A schematic cross-sectional view of another semiconductor device cut along the CC line in FIG. Figure 1 and Figure 6 As shown, in the first aspect, an embodiment of the present application provides a semiconductor device, comprising: a plurality of silicon pillars 10ˋˋ arranged in an array; an oxide insulating layer 20ˋˋ, arranged between any two adjacent silicon pillars 10ˋˋ; a plurality of bit lines 30ˋˋ, wherein the bit lines 30ˋˋ are arranged on one side of the silicon pillars 10ˋˋ; and a first insulating layer 40ˋˋ, wherein the first insulating layer 40ˋˋ is arranged on a side of the bit lines 30ˋˋ away from the silicon pillars 10ˋˋ.

[0087] It should be noted that if Figure 5 The semiconductor device shown is Figure 1 The structure of the semiconductor device shown in FIG. 1 is similar, for example, the semiconductor device further includes a hollow dielectric layer 50ˋˋ, the hollow dielectric layer 50ˋˋ is arranged on a side of the first insulating layer 40ˋˋ away from the silicon pillars 10ˋˋ, and fills the gaps between the silicon pillars 10ˋˋ, the gaps between the bit lines 30ˋˋ, and the gaps between the first insulating layers 40ˋˋ; the hollow dielectric layer 50ˋˋ includes a plurality of air gaps 51ˋˋ, at least one air gap 51ˋˋ is arranged between any two adjacent bit lines 30ˋˋ, and the air gap 51ˋˋ includes a closing portion 52ˋˋ and a uniform opening portion 53 ˋˋ; the bit line 30ˋˋ includes a first film layer 31ˋˋ, and the first insulating layer 40ˋˋ is arranged on the surface of the first film layer 31ˋˋ on the side away from the oxide insulating layer 20ˋˋ, or the bit line 30ˋˋ includes a first film layer and a second film layer stacked in sequence on one side of the silicon pillar 10ˋˋ, wherein the second film layer is provided with a groove on the side away from the first film layer 31ˋˋ, and the groove is filled with a third film layer; the first insulating layer 40ˋˋ is arranged on the surfaces of the second film layer and the third film layer on the side away from the first film layer 31ˋˋ, or the same parts are not repeated.

[0088] The difference is that the material of the first insulating layer 40 ″″ is the same as the material of the oxidized insulating layer 20 ″″.

[0089] In the semiconductor device provided in the present application, since the material of the first insulating layer 40"" is the same as that of the oxidized insulating layer 20"" , the first insulating layer 40"" can be prepared using existing materials without increasing the types of materials, thereby reducing production costs.

[0090] Figure 7 A cross-sectional schematic diagram of another semiconductor device corresponding to different steps provided in some embodiments of the present application. Figure 1 , Figure 6 and Figure 7As shown, in a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising the following steps:

[0091] A plurality of silicon pillars 10 ' ' are formed in an array, and an oxide insulating layer 20 ' ' is formed between the silicon pillars 10 ' ' ;

[0092] A bit line 30"" is formed on one side of each of the silicon pillars 10"";

[0093] Forming a first insulating layer 40"" on a side of the bit line 30"" away from the silicon pillar 10"";

[0094] A hollow dielectric layer 50 '' is formed on a side of the first insulating layer 40 '' away from the bit line 30 ''.

[0095] In some embodiments of the present application, in the step of forming a plurality of silicon pillars 10 '' arranged in an array and forming an oxidized insulating layer 20 '' between the silicon pillars 10 '', a surface of the oxidized insulating layer 20 '' is flush with a surface of the silicon pillars 10 ''.

[0096] In some embodiments of the present application, before the step of forming a bit line 30ˋˋ on one side of each silicon pillar 10ˋˋ, the step also includes: removing a portion of the oxidized insulating layer 20ˋˋ to expose at least a portion of the silicon pillar 10ˋˋ; forming a sacrificial layer 100 on one side of the oxidized insulating layer 20ˋˋ, and the surface of the sacrificial layer 100 is flush with the surface of the silicon pillar 10ˋˋ; removing a portion of the silicon pillar 10ˋˋ, so that the sacrificial layer 100 and the silicon pillar 10ˋˋ form a plurality of third groove structures 101.

[0097] In some embodiments of the present application, in the step of forming a bit line 30 '' on one side of each of the silicon pillars 10 '', the bit line 30 '' is formed in the third groove structure 101 , and the sacrificial layer 100 protrudes from the bit line 30 ''.

[0098] In some embodiments of the present application, in the step of forming a first insulating layer 40"" on a side of the bit line 30"" away from the silicon pillar 10"" , a surface of the first insulating layer 40"" on a side away from the silicon pillar 10"" is flush with a surface of the sacrificial layer 100 , and the first insulating layer 40"" is made of the same material as the oxidized insulating layer 20"" .

[0099] In some embodiments of the present application, before forming the hollow dielectric layer 50"" on the side of the first insulating layer 40"" away from the bit line 30"" , the following step is further included: removing the sacrificial layer 100 to expose at least a portion of the silicon pillar 10"" .

[0100] In some embodiments of the present application, in the step of forming a hollow dielectric layer 50"ˋ" on a side of the first insulating layer 40"ˋ" facing away from the bit line 30"ˋ" , the hollow dielectric layer 50"ˋ" fills the gaps between the silicon pillars 10"ˋ" , the gaps between the bit lines 30"ˋ" and the gaps between the first insulating layers 40"ˋ" .

[0101] In the method for preparing a semiconductor device provided in an embodiment of the present application, the sacrificial layer 100 can be arranged so that the sacrificial layer 100 and the silicon pillar 10ˋˋ form a plurality of third groove structures 101, so that the first insulating layer 40ˋˋ can be prepared by using the same material as the oxidized insulating layer 20ˋˋ, thereby achieving the preparation of the first insulating layer 40ˋˋ by using existing materials without increasing the types of materials, thereby reducing production costs.

[0102] In a third aspect, an embodiment of the present application further provides a storage system, the storage system comprising a memory, the memory being the semiconductor device described in any one of the above or a part of the semiconductor device.

[0103] In summary, the present application provides a semiconductor device and a preparation method thereof, and a memory system, wherein the semiconductor device includes: a plurality of silicon pillars arranged in an array; an oxidized insulating layer arranged between any two adjacent silicon pillars; a plurality of bit lines, wherein the bit lines are arranged on one side of the silicon pillars; and a first insulating layer, wherein the first insulating layer is arranged on the side of the bit lines away from the silicon pillars. In the semiconductor device provided by the present application, an isolation structure for reducing coupling capacitance can be formed on the oxidized insulating layer between two adjacent bit lines, and since the first insulating layer is arranged on the side of the bit lines away from the silicon pillars, the gap between the first insulating layers arranged on the side of the two adjacent bit lines away from the silicon pillars can be further utilized to increase the setting space of the isolation structure, thereby reducing the coupling capacitance between the bit lines, improving the sensing tolerance of the semiconductor device, and enhancing the device performance.

[0104] The semiconductor device and its preparation method and memory system provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A plurality of silicon pillars arranged in an array; An oxidized insulating layer is disposed between any two adjacent silicon pillars; a plurality of bit lines, the bit lines being arranged on one side of the silicon pillar; and A first insulating layer is disposed on a side of the bit line away from the silicon pillar.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a hollow dielectric layer, which is arranged on a side of the first insulating layer away from the silicon pillars and fills the gaps between the silicon pillars, the gaps between the bit lines and the gaps between the first insulating layers.

3. The semiconductor device according to claim 2, characterized in that The hollow dielectric layer includes a plurality of air gaps, and at least one of the air gaps is disposed between any two adjacent bit lines.

4. The semiconductor device according to claim 1, wherein: The bit line includes a first film layer and a second film layer stacked in sequence on one side of the silicon pillar, wherein a groove is provided on the side of the second film layer facing away from the first film layer, and the groove is filled with a third film layer; the first insulating layer is provided on the surface of the second film layer and the third film layer facing away from the first film layer.

5. The semiconductor device according to claim 4, characterized in that The first film layer includes a silicon metal compound, the second film layer includes a titanium nitride compound, and the material of the third film layer includes tungsten.

6. The semiconductor device according to claim 1, wherein: The bit line includes a first film layer, and the first insulating layer is disposed on a surface of the first film layer at a side away from the oxidized insulating layer.

7. The semiconductor device according to claim 6, characterized in that The first insulating layer includes an oxide of the material of the first film layer.

8. The semiconductor device according to claim 4 or 6, characterized in that: The first insulating layer includes non-metal nitride.

9. The semiconductor device according to claim 4 or 6, characterized in that: The material of the first insulating layer is the same as that of the oxidized insulating layer.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a plurality of silicon pillars arranged in an array, and forming an oxide insulating layer between the silicon pillars; forming a bit line on one side of each of the silicon pillars; forming a first insulating layer on a side of the bit line away from the silicon pillar; A hollow dielectric layer is formed on a side of the first insulating layer away from the bit line.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: In the step of forming a plurality of silicon pillars arranged in an array and forming an oxidized insulating layer between the silicon pillars, the oxidized insulating layer and the silicon pillars form a plurality of first groove structures; In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the first groove structure, and the oxidized insulating layer protrudes from the bit line; In the step of forming a first insulating layer on a side of the bit line away from the silicon pillar, a surface of the first insulating layer on a side away from the silicon pillar is flush with a surface of the oxidized insulating layer; Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the following steps: removing a portion of the oxidized insulating layer to expose at least a portion of the silicon pillar; In the step of forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

12. The method for manufacturing a semiconductor device according to claim 10, characterized in that: In the step of forming a plurality of silicon pillars arranged in an array and forming an oxidized insulating layer between the silicon pillars, the oxidized insulating layer and the silicon pillars form a plurality of second groove structures; In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the second groove structure; In the step of forming a first insulating layer on a side of the bit line away from the silicon pillar, a surface of the bit line is oxidized so that a portion of the bit line is transformed to form the first insulating layer; Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the following steps: removing a portion of the oxidized insulating layer to expose at least a portion of the silicon pillar; In the step of forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

13. The method for manufacturing a semiconductor device according to claim 10, characterized in that: Before the step of forming a bit line on one side of each silicon pillar, the method further includes: removing part of the oxidized insulating layer to expose at least part of the silicon pillar; forming a sacrificial layer on one side of the oxidized insulating layer, wherein the surface of the sacrificial layer is flush with the surface of the silicon pillar; removing part of the silicon pillar to form a plurality of third groove structures between the sacrificial layer and the silicon pillar; In the step of forming a bit line on one side of each of the silicon pillars, the bit line is formed in the third groove structure, and the sacrificial layer protrudes from the bit line; In the step of forming a first insulating layer on a side of the bit line away from the silicon pillar, a surface of the first insulating layer on a side away from the silicon pillar is flush with a surface of the sacrificial layer; Before forming a hollow dielectric layer on the side of the first insulating layer away from the bit line, the method further includes the following steps: removing the sacrificial layer to expose at least a portion of the silicon pillar; In the step of forming a hollow dielectric layer on a side of the first insulating layer away from the bit line, the hollow dielectric layer fills the gaps between the silicon pillars, the gaps between the bit lines, and the gaps between the first insulating layers.

14. A storage system, characterized in that: A memory is included, and the memory is the semiconductor device according to any one of claims 1 to 9 or a part of the semiconductor device.

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