Dynamic random access memory, read operation method thereof and electronic equipment
By setting up a redundant amplifier group in the dynamic random memory, ensuring the symmetry of the control signal coupling, the problem of insufficient induction margin in the prior art is solved and the readout performance is improved.
Patent Information
- Application Number
- CN202411686762.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-14
AI Technical Summary
When existing dynamic random access memory uses sensitive amplifiers to read data, the sensing margin is poor, which affects the readout performance.
A redundant amplifier group is set up in the dynamic random memory, and connected to the end memory cell group through the remaining bit lines to ensure that the control signal coupling is symmetric.
Improves the sensing margin of dynamic random memory and improves readout performance.
Smart Images
Figure CN119626287A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memory, and in particular to a dynamic random access memory and a read operation method thereof, and an electronic device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that is widely used in various fields due to its fast storage speed and high integration.
[0003] The sense amplifier (SA) is an important component of dynamic random access memory. Its main function is to amplify the small signal on the bit line to perform read or write operations.
[0004] However, the existing dynamic random access memory has a poor sensing margin when using a sense amplifier to read data, thereby affecting the read performance of the dynamic random access memory. Summary of the invention
[0005] The problem to be solved by the present invention is: how to increase the sensing margin of a dynamic random access memory to improve the read performance of the dynamic random access memory.
[0006] In order to solve the above problems, an embodiment of the present invention provides a dynamic random access memory, wherein the dynamic random access memory comprises:
[0007] Two or more storage cell groups, each storage cell group including at least one row of storage cells;
[0008] A sense amplifier group located between adjacent memory cell groups, each sense amplifier group comprising a row of sense amplifiers, wherein the sense amplifiers are connected to memory cells in the same column of the adjacent memory cell group via bit lines;
[0009] and a redundant amplifier group connected to the end storage cell groups of the two or more storage cell groups through the remaining bit lines, and used to make the control signal coupling symmetrical when performing a read operation on the dynamic random access memory;
[0010] Each of the redundant amplifier groups includes at least one redundant amplifier; the remaining bit lines are bit lines in the dynamic random access memory that are not connected to the sensitive amplifier group; and the end storage cell group is a storage cell group connected to the remaining bit lines.
[0011] In a possible embodiment, the redundant amplifier group includes: a first redundant amplifier group; the end storage cell group includes: a first storage cell group among the more than two storage cell groups; the first redundant amplifier group is connected to the first read storage cell group through the remaining bit lines.
[0012] In a possible embodiment, the redundant amplifier group includes: a second redundant amplifier group; the end storage cell group includes: a last storage cell group among the more than two storage cell groups; the second redundant amplifier group is connected to the last read storage cell group through the remaining bit lines.
[0013] In a possible embodiment, the structure of the redundant amplifier is the same as that of the sensitive amplifier.
[0014] In a possible embodiment, the redundant amplifier has a symmetrical structure.
[0015] In a possible embodiment, the redundant amplifier is composed of an amplification circuit, an offset cancellation circuit and a pre-charge circuit; wherein:
[0016] The amplifier circuit is used to amplify the signal of the redundant amplifier;
[0017] The offset cancellation circuit is used to perform offset cancellation processing on the redundant amplifier;
[0018] The pre-charging circuit is used to perform a pre-charging process on the redundant amplifier.
[0019] In a possible embodiment, the amplifier circuit has a first connection end and a second connection end, the first connection end is connected to the remaining bit lines connected to the same column of storage cells in the end storage cell group, and the second connection end is connected to the remaining bit lines connected to the adjacent column of storage cells in the end storage cell group.
[0020] The embodiment of the present invention further provides a dynamic random access memory read operation method, the method comprising:
[0021] In the process of performing a read operation on a memory cell group using the sense amplifier group, controlling the amplifiers connected to other bit lines coupled to the reference bit line of the memory cell group to perform synchronous control signal switching;
[0022] The amplifiers connected to the other bit lines coupled to the reference bit line of the memory cell group include: a redundant amplifier and a sense amplifier, or a sense amplifier and a sense amplifier.
[0023] In a possible embodiment, the control signal includes: a pre-charge control signal, an amplification control signal, and a depolarization control signal.
[0024] An embodiment of the present invention further provides an electronic device, comprising any one of the above-mentioned dynamic random access memories.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0026] By applying the solution of the present invention, a redundant amplifier group is set in a dynamic random access memory, and the redundant amplifier group is connected to the end storage unit group through the remaining bit lines. Therefore, when a read operation is performed on the dynamic random access memory, the control signal coupling has symmetry, and the induction margin of the dynamic random access memory can be improved, thereby finally improving the read performance of the dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a connection diagram of a storage array and a sense amplifier in a dynamic random access memory;
[0028] Figure 2 yes Figure 1 A simplified structural diagram of;
[0029] Figure 3 is a simplified structural diagram of a dynamic random access memory in one embodiment of the present invention;
[0030] Figure 4 is a simplified structural diagram of a dynamic random access memory in another embodiment of the present invention;
[0031] Figure 5 is a simplified structural diagram of a dynamic random access memory in another embodiment of the present invention;
[0032] Figure 6 is a schematic diagram of the structure of a redundant amplifier in an embodiment of the present invention;
[0033] Figure 7 yes Figure 6 A timing diagram of related signals of the redundant amplifier during the read operation;
[0034] Figure 8 is a schematic diagram of the structure of another redundant amplifier in an embodiment of the present invention;
[0035] Fig. 9 Is adopted Figure 7 A schematic diagram of the layout structure of the redundant amplifier corresponding to FIG.
[0036] Fig.10 Is adopted Figure 8 Schematic diagram of the layout structure corresponding to the redundant amplifier shown in FIG. DETAILED DESCRIPTION
[0037] At present, the storage array in the dynamic random access memory is formed by a plurality of storage cells distributed in an array. The storage array can be divided into n groups according to rows, where n≥2 and n is an integer. Each storage cell group is called a MAT. The dynamic random access memory is usually provided with n-1 sense amplifier groups, each sense amplifier group can be connected to a storage cell group, so as to perform a read or write operation on the connected storage cell group.
[0038] Figure 1 The figure is a schematic diagram of the connection between the storage array and the sense amplifier in a dynamic random access memory. Figure 1 The storage array of the dynamic random access memory may include M columns, which may be divided into four groups according to rows, namely, a first storage cell group MAT0, a second storage cell group MAT1, a third storage cell group MAT2, and a fourth storage cell group MAT2b. The dynamic random access memory is also provided with three sense amplifier groups, namely, a first sense amplifier group SA0, a second sense amplifier group SA1, and a third sense amplifier group SA2, each sense amplifier group includes M sense amplifiers, and each column of storage cells corresponds to one sense amplifier.
[0039] Specifically, each storage unit is provided with two bit lines, namely, a first bit line bl and a second bit line bl_n. Each storage unit is connected to a sense amplifier through two corresponding bit lines. The sense amplifier writes data to the corresponding storage unit or reads data from the storage unit through the connected first bit line and second bit line. In the embodiment of the present invention, the first bit line bl and the second bit line bl_n only represent two different bit lines and do not have a logical relationship.
[0040] For example, refer to Figure 1 In the fourth memory cell group MAT2b, the first column of memory cells has a first bit line bl <0> and the second bit line bl_n <0> The second column of memory cells has a first bit line bl <1> and the second bit line bl_n <1> The third column of memory cells has a first bit line bl <2> and the second bit line bl_n <2> The fourth column of memory cells has a first bit line bl <3> and the second bit line bl_n <3> The Mth column of memory cells has a first bit line bl <m-1>and the second bit line bl_n <m-1>.
[0041] Each column of memory cells in the fourth memory cell group MAT2b is connected to the second bit line connection terminal of the sense amplifier in the same column in the first sense amplifier group SA0 via the second bit line.
[0042] Each column of storage cells in the first storage cell group MAT0 is connected to the first bit line connection terminal of the sense amplifier in the same column in the first sense amplifier group SA0 through a first bit line. Each column of storage cells in the first storage cell group MAT0 is connected to the second bit line connection terminal of the sense amplifier in the same column in the second sense amplifier group SA1 through a second bit line.
[0043] Each column of memory cells in the second memory cell group MAT1 is connected to the first bit line connection terminal of the sense amplifier in the same column in the second sense amplifier group SA1 through the first bit line. Each column of memory cells in the second memory cell group MAT1 is connected to the second bit line connection terminal of the sense amplifier in the same column in the third sense amplifier group SA2 through the second bit line.
[0044] Each column of memory cells in the third memory cell group MAT2 is connected to the first bit line connection terminal of the sense amplifier in the same column in the third sense amplifier group SA2 via the first bit line.
[0045] Figure 2 for Figure 1 A simplified structural diagram of Figure 2 , the red solid line represents the first bit line, the blue solid line represents the second bit line, when the dynamic random access memory is read, the first bit line of the fourth storage cell group MAT2b and the second bit line of the third storage cell group MAT2 are both connected to the precharge voltage VBLP. Each sense amplifier group performs a read operation on each storage cell group according to the first bit line and the second bit line.
[0046] Specifically, the first sense amplifier group SA0 and the second sense amplifier group SA1 are controlled to be turned on, and the first bit line connected between the first sense amplifier group SA0 and the first storage cell group MAT0, and the second bit line connected between the second sense amplifier group SA1 and the first storage cell group MAT0, are used to implement the read operation of the first storage cell group MAT0. At this time, the second bit line connected between the first sense amplifier group SA0 and the fourth storage cell group MAT2b, and the first bit line connected between the second sense amplifier group SA1 and the second storage cell group MAT1 are used as reference bit lines.
[0047] The second sense amplifier group SA1 and the third sense amplifier group SA2 are controlled to be turned on, and based on the first bit line connected between the second sense amplifier group SA1 and the second storage cell group MAT1, and the second bit line connected between the third sense amplifier group SA2 and the second storage cell group MAT1, a read operation on the second storage cell group MAT1 is implemented. At this time, the second bit line connected between the second sense amplifier group SA1 and the first storage cell group MAT0, and the first bit line connected between the third sense amplifier group SA2 and the third storage cell group MAT2 are used as reference bit lines.
[0048] The first sense amplifier group SA0 and the third sense amplifier group SA2 are controlled to be turned on, and based on the second bit line connected between the first sense amplifier group SA0 and the fourth storage cell group MAT2b, the fourth storage cell group MAT2b is read out. At this time, since only one bit line of the first sense amplifier group SA0 is connected to the fourth storage cell group MAT2b, only half of the data of the fourth storage cell group MAT2b can be read out. Based on the first bit line connected between the third sense amplifier group SA2 and the third storage cell group MAT2, the third storage cell group MAT2 is read out. At this time, since only one bit line of the third sense amplifier group SA2 is connected to the third storage cell group MAT2, only half of the data of the third storage cell group MAT2 can be read out. The data read out from the fourth storage cell group MAT2b and the data read out from the third storage cell group MAT2 are combined as the result of this readout. In this process, the remaining bit lines of the fourth storage cell group MAT2b and the third storage cell group MAT2 are used as reference bit lines.
[0049] During the above-mentioned read operation, the switching of each control signal will generate coupling to the adjacent bit line. Figure 2 Taking the reading of the second storage cell group MAT1 as an example, since the second storage cell group MAT1 is connected to the second sense amplifier group SA1 through the first bit line bl (SA1), and the second storage cell group MAT1 is connected to the third sense amplifier group SA2 through the second bit line bl_n (SA2), the voltages on the second bit line bl_n (SA2) and the second bit line bl_n (SA1) both need to be switched by the control signal, and the switching of the control signal will generate coupling between the first bit line bl (SA1) and the second bit line bl_n (SA2), and between the first bit line bl (SA1) and the second bit line bl_n (SA1), respectively, and will also generate coupling between the first bit line bl (SA2) and the second bit line bl_n (SA2), while the second bit line bl_n (BLP) remains connected to the pre-charge voltage, so no coupling is generated on the second bit line bl_n (BLP), that is, no coupling is generated between the first bit line bl (SA2) and the second bit line bl_n (BLP).
[0050] Whether the coupling strength of each bit line is equal will affect the accuracy of reading. When performing a read operation on the second storage cell group MAT1, since there is no coupling between the first bit line bl (SA2) and the second bit line bl_n (BLP), the coupling strength of the first bit line bl (SA2) is less than the coupling strength of the first bit line bl (SA1), so the coupling strength of the first bit line bl (SA2) and the first bit line bl (SA1) are not equal, that is, the coupling of the control signal in the same storage cell group is asymmetric, which will affect the inductive margin of the dynamic random access memory and further affect the accuracy of reading.
[0051] To address this problem, the present invention provides a dynamic random access memory, which is provided with not only a sensitive amplifier group but also a redundant amplifier group. Through the redundant amplifier group, when a read operation is performed on the dynamic random access memory, the control signal coupling can be made symmetrical, thereby increasing the inductive margin of the dynamic random access memory and improving the read performance of the dynamic random access memory.
[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0053] An embodiment of the present invention provides a dynamic random access memory, which may include:
[0054] Two or more storage cell groups, each storage cell group including at least one row of storage cells;
[0055] A sense amplifier group located between adjacent memory cell groups, each sense amplifier group comprising a row of sense amplifiers, wherein the sense amplifiers are connected to memory cells in the same column of the adjacent memory cell group via bit lines;
[0056] and a redundant amplifier group connected to an end storage cell group of the two or more storage cell groups through a remaining bit line, for making control signal coupling symmetrical when performing a read operation on the end storage cell group;
[0057] Each of the redundant amplifier groups includes at least one redundant amplifier; the remaining bit lines are bit lines in the dynamic random access memory that are not connected to the sensitive amplifier group; and the end storage cell group is a storage cell group connected to the remaining bit lines.
[0058] By setting up a redundant amplifier group, when performing a read operation on the dynamic random access memory, the coupling strength between each bit line of the same storage unit group and other bit lines can be equal, so that the control signal coupling has symmetry, and finally the read performance of the dynamic random access memory is improved.
[0059] In a specific implementation, the memory cells may be divided into a plurality of memory cell groups according to the number of rows. Each memory cell group may include only one row of memory cells, or may include two or more rows of memory cells. Viewed along the column direction of the memory cells, the end memory cell group is the memory cell group connected to the remaining bit lines.
[0060] In one embodiment, the end storage cell group may include: the first storage cell group among two or more storage cell groups. The first storage cell group may be the first storage cell group read in the dynamic random access memory, or may not be the first storage cell group read, and the specific order of being read is not limited. Regardless of the order of being read, the first storage cell group is the first storage cell group at one end of all storage cell groups in the column direction.
[0061] Figure 3 FIG. 1 is a simplified schematic diagram of a dynamic random access memory according to an embodiment of the present invention. Figure 3 In one embodiment, along the column direction A, the dynamic random access memory may include four memory cell groups, namely, a first memory cell group MAT31, a second memory cell group MAT32, a third memory cell group MAT33, and a fourth memory cell group MAT34. A first sensitive amplifier group SA30 is disposed between the first memory cell group MAT31 and the second memory cell group MAT32, a second sensitive amplifier group SA31 is disposed between the second memory cell group MAT32 and the third memory cell group MAT33, and a third sensitive amplifier group SA32 is disposed between the third memory cell group MAT33 and the fourth memory cell group MAT34.
[0062] At this time, the first storage cell group of the dynamic random access memory is the first storage cell group MAT31. The first storage cell group MAT31 has a remaining first bit line bl (SA_dum0). The dynamic random access memory may include a first redundant amplifier group SA_dum0, and the first redundant amplifier group SA_dum0 includes a plurality of first redundant amplifiers. Each first redundant amplifier has a bit line connection terminal.
[0063] In the prior art, the remaining first bit line bl (SA_dum0) is connected to the precharge voltage. In the embodiment of the present invention, the remaining first bit line bl (SA_dum0) is connected to the bit line connection terminal of the corresponding first redundant amplifier, so that when the storage unit of the column connected to the first bit line bl (SA_dum0) is read, the first redundant amplifier is used to synchronously switch the control signal, so that the two bit lines connected to the storage unit group to be read have equal coupling strength, thereby ensuring the symmetry of the control signal coupling and improving the read performance.
[0064] In another embodiment, the end storage cell group may include: the last storage cell group in more than two storage cell groups. The last storage cell group may be the last storage cell group read in the dynamic random access memory, or may be a non-last storage cell group read, and the specific order of reading is not limited. Regardless of the order of reading, the last storage cell group is the first storage cell group at the other end of all storage cell groups in the column direction. The last storage cell group and the first storage cell group are located at opposite ends of all storage cell groups in the dynamic random access memory.
[0065] Figure 4 FIG. 1 is a simplified schematic diagram of a dynamic random access memory in another embodiment of the present invention. Figure 4 Among all the memory cell groups shown, the last memory cell group is the memory cell group 34. The memory cell group 34 has a remaining second bit line bl_n (SA_dum1).
[0066] At this time, the dynamic random access memory may include a second redundant amplifier group SA_dum1. The second redundant amplifier group SA_dum1 includes a plurality of second redundant amplifiers. Each second redundant amplifier has a bit line connection terminal.
[0067] In the prior art, the remaining second bit lines bl_n (SA_dum1) are connected to the precharge voltage. In the embodiment of the present invention, the remaining second bit lines bl_n (SA_dum1) are connected to the bit line connection terminal of the corresponding second redundant amplifier, so that when the storage unit of the column connected to the second bit line bl (SA_dum0) is read, the second redundant amplifier is used to synchronously switch the control signal, so that the two bit lines connected to the storage unit group to be read have equal coupling strength, thereby ensuring the symmetry of the control signal coupling and improving the read performance.
[0068] In one embodiment, referring to Figure 5 The redundant amplifier group may include the first redundant amplifier group SA_dum0 and the second redundant amplifier group SA_dum1 at the same time. In this case, the dynamic random access memory may be provided with the first redundant amplifier group SA_dum0 and the second redundant amplifier group SA_dum1 at the same time, thereby ensuring the symmetry of the control signal coupling to the greatest extent, and thus improving the read performance to the greatest extent.
[0069] by Figure 5 For example, when the second storage cell group MAT31 needs to read data, the first sense amplifier group SA30 and the first sense amplifier group SA31 can be controlled to be turned on, and the first redundant amplifier group SA_dum0 and the third sense amplifier group SA32 can be controlled to switch control signals. At this time, the first bit lines on the first storage cell group MAT31 and the third storage cell group MAT33 are used as reference bit lines.
[0070] When data needs to be read from the third storage cell group, the second sense amplifier group SA31 and the third sense amplifier group SA32 can be controlled to be turned on, and the first sense amplifier group SA30 and the second redundant amplifier group SA_dum1 can be controlled to synchronously switch control signals, and the first bit lines on the second storage cell group MAT32 and the fourth storage cell group MAT34 are used as reference bit lines.
[0071] When data needs to be read from the first and fourth storage cell groups MAT31 and MAT34, the first and third sense amplifier groups SA30 and SA32 can be controlled to be turned on, and the bit lines connected to the redundant amplifiers on the first and fourth storage cell groups MAT31 and MAT34 are used as reference bit lines.
[0072] In a specific implementation, the redundant amplifier can be implemented using a variety of structures, which are not limited here.
[0073] In an embodiment of the present invention, the structure of the redundant amplifier is the same as that of the sense amplifier.
[0074] Specifically, in one embodiment, the redundant amplifier and the sense amplifier are both symmetrical structures.
[0075] Reference Figure 6 , the redundant amplifier may include: an amplification circuit, an offset elimination circuit, a pre-charge circuit and a signal input circuit. Wherein, the amplification circuit may include: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6, and the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 form a cross-coupling circuit. The offset elimination circuit may include: a seventh transistor Q7 and an eighth transistor Q8. The pre-charge circuit may include a first pre-charge transistor Y1 and a second pre-charge transistor Y2. The signal transmission circuit may include a first transmission transistor T1 and a second transmission transistor T2.
[0076] In a specific implementation, the first transistor Q1 and the second transistor Q2 can be PMOS tubes, and the remaining transistors can be implemented using NMOS tubes. blsb represents an amplification control signal, bleq represents a pre-charge control signal, vblp represents a pre-charge power supply signal, blsa represents a debiasing control signal, Isae represents a transmission control signal, Idl represents a target transmission node, Idl_n represents a target complementary transmission node, bl represents a first bit line, bl_n represents a second bit line, sa1 represents a first coupling node, and sa2 represents a second coupling node. Among them, the voltage value of the pre-charge power supply signal vblp is a pre-charge voltage. The amplified signal is transmitted to the target transmission node Idl and the target complementary transmission node Idl_n. In addition, SP1 and SN represent power supply signals respectively, and the power supply signal SP1 and the power supply signal SN are connected to an external power control switch.
[0077] The gates of the fifth transistor Q5 and the sixth transistor Q6 receive the amplification control signal blsb. When the fifth transistor Q5 and the sixth transistor Q6 are turned on (or called turned on), the fifth transistor Q5 and the sixth transistor Q6 can be used as transmission gates. In this way, the cross-coupling circuit (the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4), the fifth transistor Q5 and the sixth transistor Q6 form an inverter latch structure connected head to tail for amplifying the signal.
[0078] In a specific implementation, the pre-charging circuit can provide a charging voltage to the first coupling node sa1 and the second coupling node sa2, thereby enabling the offset cancellation circuit to perform offset cancellation processing according to the voltages of the first coupling node sa1 and the second coupling node sa2.
[0079] Figure 7 for Figure 6 The timing diagram of the related signals of the redundant amplifier during the read operation. Figure 7 The S1 stage is the precharge stage (PreCharge, EQ), the S2 stage is the offset cancellation stage (Offset Cancellation, OC), the S3 stage is the charge sharing stage (Charge Sharing), the S4 stage is the amplification stage (Sensing), and the S5 stage is the stage of reading the amplified signal to the post-amplifier (Send to LSA).
[0080] In the S4 stage, the seventh transistor Q7, the eighth transistor Q8, the first pre-filling transistor Y1 and the second pre-filling transistor Y2, the first transmission transistor T1 and the second transmission transistor T2 are in the off state, and the remaining transistors are in the on state. In the S5 stage, the seventh transistor Q7, the eighth transistor Q8, the first pre-filling transistor Y1 and the second pre-filling transistor Y2 are in the off state, and the remaining transistors are in the on state. The amplified signal is sent to the post-stage amplifier through the first transmission transistor T1 and the second transmission transistor T2.
[0081] use Figure 6 As shown in the redundant amplifier, assuming that a storage cell group includes M columns of storage cells, a redundant amplifier group should be provided with M redundant amplifiers, and the gate of the third transistor Q3 of each redundant amplifier is connected to the remaining second bit lines of the storage cells in the same column of the first storage cell group, or the gate of the fourth transistor Q4 of each redundant amplifier is connected to the remaining first bit lines of the storage cells in the same column of the first storage cell group.
[0082] For example, in Figure 5 In the DRAM shown, the gate of the fourth transistor Q4 in the first redundant amplifier in the first redundant amplifier group SA_dum0 is connected to the remaining first bit line bl (SA_dum0), and the gate of the third transistor Q3 in the second redundant amplifier in the second redundant amplifier group SA_dum1 is connected to the remaining second bit line bl_n (SA_dum1).
[0083] In a specific implementation, the control signals that have a greater impact on the coupling strength of the remaining bit lines are the pre-charge control signal bleq, the amplification control signal blsb, and the debiasing control signal blsa. In the read operation phase, these three control signals are all switched from a high level to a low level. Therefore, when the sensitive amplifier is used to read the data "1", it will affect the sensing margin of the memory, thereby affecting the accuracy of the readout.
[0084] To this end, in a specific implementation, when controlling the redundant amplifier to switch the synchronous signal, at least the pre-charge control signal bleq, the amplification control signal blsb and the debiasing control signal blsa are controlled to switch the synchronous signal, thereby reducing the impact on the memory inductive margin.
[0085] In another embodiment of the present invention, the redundant amplifier is composed of an amplifier circuit, an offset cancellation circuit and a pre-charge circuit, wherein the amplifier circuit is used to amplify the signal of the redundant amplifier, the offset cancellation circuit is used to perform offset cancellation on the redundant amplifier, and the pre-charge circuit is used to perform pre-charge on the redundant amplifier.
[0086] Figure 8 Schematic diagram of a redundant amplifier. Figure 8 ,and Figure 7 The redundant amplifier structure is different in that Figure 8 In the structure shown, the redundant amplifier does not include a signal input circuit, that is, does not include Figure 7 At this time, the sources of the first transistor Q1 and the second transistor Q2 are both connected to the precharge power signal vblp, and the sources of the third transistor Q3 and the fourth transistor Q4 are also connected to the precharge power signal vblp, so that the entire redundant amplifier is powered by the precharge power signal vblp.
[0087] exist Figure 8 In the structure shown, the gate of the third transistor Q3 serves as the first connection terminal bl0, and the gate of the fourth transistor Q4 serves as the second connection terminal bl1. The first connection terminal bl0 and the second connection terminal bl1 can be connected to the remaining bit lines of two adjacent columns of memory cells in the end memory cell group.
[0088] Fig. 9 To adopt Figure 7 FIG. 1 is a schematic diagram of a layout structure corresponding to a redundant amplifier shown in FIG. Fig.10 To adopt Figure 8 FIG. 1 is a schematic diagram of a layout structure corresponding to a redundant amplifier shown in FIG.
[0089] Reference Fig. 9 , during the layout process, if you use Figure 7 The redundant amplifier shown in Figure 7 The redundant amplifier in the redundant amplifier group is rotated 90 degrees counterclockwise and then connected to a remaining bit line. Taking the remaining bit line as the remaining first bit line bl as an example, the first redundant amplifier in the redundant amplifier group is connected to the remaining first bit line bl <0> The second redundant amplifier is connected to the remaining first bit line bl <1> The third redundant amplifier is connected to the remaining first bit line bl <2> The fourth redundant amplifier is connected to the remaining first bit line bl <3> Connect, ... In this way, each column of storage cells corresponds to a redundant amplifier. When each storage cell group includes M columns of storage cells, M redundant amplifiers need to be provided in one redundant amplifier group.
[0090] Reference Fig.10 , during the layout process, if you use Figure 8 For the redundant amplifier shown in FIG. 1 , there is no need to rotate the redundant amplifier, and the first connection terminal bl0 and the second connection terminal bl1 in the redundant amplifier can be directly connected to the corresponding remaining bit lines.
[0091] Taking the remaining bit line as the remaining first bit line bl as an example, the first connection terminal bl0 of the first redundant amplifier in the redundant amplifier group is connected to the remaining first bit line bl of the first storage unit in the end storage unit group. <0> The second connection terminal bl1 of the first redundant amplifier in the redundant amplifier group is connected to the remaining first bit line bl of the second storage unit in the end storage unit group. <1> The first connection terminal bl0 of the second redundant amplifier in the redundant amplifier group is connected to the remaining first bit line bl of the second storage cell in the end storage cell group. <2> The second connection terminal bl1 of the second redundant amplifier in the redundant amplifier group is connected to the remaining first bit line bl of the third storage cell in the end storage cell group. <3> In this way, every two columns of storage cells correspond to a redundant amplifier. When each storage cell group includes M columns of storage cells, M / 2 redundant amplifiers need to be provided in one redundant amplifier group.
[0092] For example, in Figure 5 In the embodiment, only M / 2 first redundant amplifiers may be provided in the first redundant amplifier group, and each first redundant amplifier is connected to the remaining first bit lines of two adjacent columns of storage cells in the first storage cell group. Only M / 2 second redundant amplifiers may be provided in the second redundant amplifier group, and each second redundant amplifier is connected to the remaining second bit lines of two adjacent columns of storage cells in the last storage cell group.
[0093] use Figure 8 The structure shown in FIG. 1 forms a redundant amplifier group, which is different from the one using Figure 7 The redundant amplifiers shown in FIG. 1 form a redundant amplifier group, which can save half of the circuit area.
[0094] The embodiment of the present invention further provides a dynamic random access memory read operation method, the method comprising:
[0095] In the process of performing a read operation on a memory cell group by using the sense amplifier group, other amplifiers connected to other bit lines coupled to the reference bit line of the memory cell group are controlled to perform synchronous control signal switching.
[0096] The amplifiers connected to the other bit lines coupled to the reference bit line of the memory cell group include: a redundant amplifier and a sensitive amplifier, or a sensitive amplifier and a sensitive amplifier.
[0097] In a specific implementation, the storage cell group of the dynamic random access memory may include: an end storage cell group and a middle storage cell group. The end storage cell group is a storage cell group located at one end of the storage array, and the middle storage cell group is a storage cell group located in the middle of the storage array. Figure 5 In the embodiment, the first storage cell group MAT31 and the fourth storage cell group MAT34 are end storage cell groups, and the second storage cell group MAT32 and the third storage cell group MAT33 are middle storage cell groups.
[0098] In a specific implementation, the amplifier connected to other bit lines coupled to the reference bit line of the memory cell group can be determined based on the memory cell group actually read, as long as the coupling strengths of the two reference bit lines on the read memory cell group are equal.
[0099] When a read operation is performed on the intermediate storage cell group, the sense amplifier group used to perform the read operation on the intermediate storage cell group can be controlled to be turned on, while other amplifier groups having coupling strength with the bit lines of the intermediate storage cell group are controlled to switch control signals synchronously.
[0100] For example, when reading data from the second storage cell group MAT32, the first sensitive amplifier group SA30 and the second sensitive amplifier group SA31 are controlled to be turned on, and the first redundant amplifier group SA_dum0 and the third storage cell group MAT33 are controlled to synchronously switch control signals. At this time, the reference bit lines of the second storage cell group MAT32 are the remaining first bit line bl (SA_dum0) and the first bit line bl (SA31). There is coupling between the remaining first bit line bl (SA_dum0) and the second bit line bl_n (SA30). There is coupling between the first bit line bl (SA31) and the second bit line bl_n (SA32). The coupling strength of the two reference bit lines of the second storage cell group MAT32 is equal, thereby making the data reading of the second storage cell group MAT32 more accurate.
[0101] When reading data from the third storage cell group MAT33, the second sense amplifier group SA31 and the third sense amplifier group SA32 are controlled to be turned on, and the second redundant amplifier group SA_dum1 and the first sense amplifier group SA30 are controlled to switch control signals synchronously. The reference bit lines of the third storage cell group MAT33 are the first bit line bl (SA30) and the first bit line bl (SA32). At this time, the first bit line bl (SA30) is coupled with the second bit line bl_n (SA31) and the second bit line bl_n (SA30), the first bit line bl (SA32) is coupled with bl_n (SA32) and the remaining second bit lines bl (SA_dum1), and the coupling strengths of the first bit line bl (SA30) and the first bit line bl (SA32) are equal, so that the data reading of the third storage cell group MAT33 can be more accurate.
[0102] When performing a read operation on the memory cell groups at both ends, the sense amplifier group used to perform the read operation on the middle memory cell group can be controlled to be turned on, without switching the control signal of the redundant amplifier group. At this time, the remaining bit lines of the memory cell groups at both ends are used as reference bit lines, and the coupling strengths of the two reference bit lines are both zero, thereby making the coupling strengths of the two reference bit lines equal.
[0103] For example, refer to Figure 5 When performing the read operation on the first storage cell group MAT31 and the fourth storage cell group MAT34, the first sensitive amplifier group SA30 and the third sensitive amplifier group SA32 are controlled to be turned on. At this time, the remaining first bit line bl (SA_dum0) of the first storage cell group MAT31 and the remaining second bit line bl_n (SA_dum1) of the fourth storage cell group MAT34 are used as reference bit lines, and the coupling strength of the two is zero, thereby ensuring the accuracy of the data read from the first storage cell group MAT31 and the fourth storage cell group MAT34.
[0104] In a specific implementation, when the redundant amplifier is controlled to switch the synchronous signal, at least the pre-charge control signal bleq, the amplification control signal blsb and the debiasing control signal blsa are controlled to switch the synchronous signal, thereby reducing the impact on the memory inductive margin.
[0105] Table 1 Figure 2 Dynamic random access memory and Figure 5 The dynamic random access memory senses margin when reading data "0" and "1".
[0106] Referring to Table 1, Sensing0 represents the sensing margin when reading data "0" from the dynamic random access memory, Sensing1 represents the sensing margin when reading data "1" from the dynamic random access memory, and Total margin represents the total sensing margin of the dynamic random access memory.
[0107] Table 1
[0108] Induction margin Figure 2 Figure 5 Sensing0(mV) 270 260 Sensing1(mV) 225 310 Total margin(mV) 495 570
[0109] From Table 1, we can see that Figure 5 In the dynamic random access memory, whether reading data "0" or reading data "1" from the dynamic random access memory, the sensing margin of the dynamic random access memory is improved, and when reading data "1" from the dynamic random access memory, the sensing margin of the dynamic random access memory is improved more. Therefore, the scheme of the present invention can effectively improve the sensing margin of reading data from the dynamic random access memory, especially optimize the sensing margin when reading data "1" from the dynamic random access memory.
[0110] It should be noted that when writing data into the dynamic random access memory, the redundant amplifier only needs to be powered off so that the redundant amplifier does not work, and the sense amplifier is still used to write data.
[0111] From the above content, it can be seen that the dynamic random access memory in the embodiment of the present invention, by adding redundant amplifiers on both sides of the storage unit group, can control the signal coupling to be symmetrical when performing a read operation on the dynamic random access memory, thereby improving the inductive margin of the dynamic random access memory and ultimately improving the read performance of the dynamic random access memory.
[0112] An embodiment of the present invention further provides an electronic device, which includes the dynamic random access memory of any one of the above embodiments.
[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A dynamic random access memory, characterized in that: include: Two or more storage cell groups, each storage cell group including at least one row of storage cells; A sense amplifier group located between adjacent memory cell groups, each sense amplifier group including a row of sense amplifiers, wherein the sense amplifiers are connected to memory cells in the same column of the adjacent memory cell group through bit lines; and a redundant amplifier group connected to the end storage cell groups of the two or more storage cell groups through the remaining bit lines, and used to make the control signal coupling symmetrical when performing a read operation on the dynamic random access memory; Each of the redundant amplifier groups includes at least one redundant amplifier; the remaining bit lines are bit lines in the dynamic random access memory that are not connected to the sensitive amplifier group; and the end storage cell group is a storage cell group connected to the remaining bit lines.
2. The dynamic random access memory according to claim 1, wherein: The redundant amplifier group includes: a first redundant amplifier group; the end storage cell group includes: a first storage cell group among the two or more storage cell groups; the first redundant amplifier group is connected to the first read storage cell group through the remaining bit lines.
3. The dynamic random access memory according to claim 1 or 2, characterized in that: The redundant amplifier group includes: a second redundant amplifier group; the end storage cell group includes: a last storage cell group among the two or more storage cell groups; the second redundant amplifier group is connected to the last read storage cell group through the remaining bit lines.
4. The dynamic random access memory according to claim 1, wherein: The structure of the redundant amplifier is the same as that of the sense amplifier.
5. The dynamic random access memory according to claim 1, wherein: The redundant amplifier has a symmetrical structure.
6. The dynamic random access memory according to claim 1, wherein: The redundant amplifier is composed of an amplifier circuit, an offset cancellation circuit and a pre-charge circuit; wherein: The amplifier circuit is used to amplify the signal of the redundant amplifier; The offset cancellation circuit is used to perform offset cancellation processing on the redundant amplifier; The pre-charging circuit is used to perform a pre-charging process on the redundant amplifier.
7. The dynamic random access memory according to claim 6, wherein: The amplifier circuit has a first connection end and a second connection end, the first connection end is connected to the remaining bit lines connected to the same column storage cells in the end storage cell group, and the second connection end is connected to the remaining bit lines connected to the adjacent column storage cells in the end storage cell group.
8. A read operation method of a dynamic random access memory according to any one of claims 1 to 7, characterized in that: include: In the process of performing a read operation on a storage cell group using the sense amplifier group, controlling the amplifiers connected to other bit lines coupled to the reference bit line of the storage cell group to perform synchronous control signal switching; The amplifiers connected to the other bit lines coupled to the reference bit line of the memory cell group include: a redundant amplifier and a sense amplifier, or a sense amplifier and a sense amplifier.
9. The method according to claim 8, characterized in that The control signal includes: a pre-charge control signal, an amplification control signal and a depolarization control signal.
10. An electronic device, characterized in that: A dynamic random access memory comprising any one of claims 1 to 7.