167results about How to "Realize simple structure" patented technology

The invention discloses a broadband dual-polarized antenna unit, which is used for realizing broader band characteristic. A radiating element comprises a reflective plate, a main radiating body, an upper insulating block, a lower insulating block and a balance feed device, wherein the main radiating body comprises a support body and radiating pieces; four radiating pieces and the support body form a whole, and the four radiating pieces respectively form an angle of 90 degrees with the support body; the outline of each radiating piece has a 90-degree fan shape; each radiating piece is provided with a hollowed structure and a loading section used for broadening the bandwidth and improving polarization purity; a clearance between two adjacent radiating pieces is less than 0.1 wavelength; and the radiating element adopts coupling balance feed and an integrated design that four support body bottoms are mutually short-circuited, and is fixed on the reflective plate. The broadband dual-polarized antenna unit has impedance bandwidth of over 45 percent, and has the advantages of small size, simple structure, a few components, convenience for assembly, easy production, low cost and the like.

The invention provides a frequency selection surface structure based on a stereo structure, relates to the frequency selection surface structure and solves the problems that an existing frequency selection surface of a simple structure has fewer controllable parameters and is small in gradient of a frequency response curve, poor in polarization stability and poor in miniaturization in practical application. According to the invention, four No.1 medium plates are perpendicularly spliced to form a rectangular frame, a metal film layer is coated on the inner side wall of the rectangular frame, circular through holes are formed in the No.1 medium plates, and the a metal film layer is coated on the inner side of each circular through hole; and two No.2 medium plates are respectively arranged in the rectangular frame, one pair of opposite edges of each No.2 medium plate is fixedly connected with the inner side wall of the rectangular frame, the two No.2 medium plates are perpendicularly connected along a center line to form a cross structure, metal film strips are respectively arranged on the lower surface of a left arm, the upper surface of a right arm, the left side surface of an upper arm and the right side surface of the lower arm of the cross resonance structure. The frequency selection surface structure is applicable to manufacturing and usage of an antenna cover.

The invention claims to protect a chaotic circuit and its realization method for generating multi-surrounding coil waves, and relates to a chaotic circuit in secure communication. The chaotic circuit is composed of four parts: fourth-order autonomous circuit N1, adding amplifier N2, piecewise function sequence generator N3 and inverting amplifier N4. The piecewise function sequence generator constructs the piecewise function of the turning point, creates sub-circuits, and controls the number of coils generated by the chaotic circuit in the V2 and V3 directions; by adjusting the Rncc value of the piecewise function sequence generator, the volume of the scroll is adjusted. size. The circuit design method of the present invention is simple, the chaotic signal generation circuit is flexible, and can provide a random number of chaotic signal circuits with continuous coils around the coils. The number of coils around the coils can be controlled by switching the linkage switch, and two coils around the coils, respectively, can be generated. Three-surrounding wire coil wave, etc., and has good performance, and can be widely used in secure communication.

The invention provides a digital-shaping filtering method for a continuous and variable speed. The digital-shaping filtering method for the continuous and variable speed comprises the steps that (1) a one-time data clock signal A1 and an N-time data clock signal AN are generated through a digital NCO, (2) an input signal is received according to the data clock signal A1, (3) N-time zero-fill interpolation is conducted on the received signal by means of the data clock signal AN, (4) the signal subjected to interpolation is filtered by means of a digital shaping filter, and (5) variable-sampling-rate interpolation filtering is conducted on the signal subjected to shaping filtering. According to the continuous variable-speed digital-shaping filtering method, the shaping filter with the fixed coefficient and an interpolation filter with a variable coefficient are used for shaping filtering and interpolation filtering respectively, shaping filtering and interpolation filtering of different speed signals can be achieved, the method can be applied to a digital modulator with continuous and variable data speed, the filtering method is easy to realize, hardware resource consumption is low, and practicability is high.

The invention relates and discloses an interpolating digital filter device which is applied to a wireless medium range sensor network physical layer, comprising an interpolating digital filter module based on FIR (Finite impulse response filter) and an interpolating digital filter module based on CIC (Cascaded integrator-comb filter). The interpolating digital filter module based on FIR comprises a shift register time delay module, a multiplication module, a coefficient selector module, and an accumulator module. Wherein, the accumulator module comprises a register module and an adder module. The interpolating digital filter module based on CIC comprises a pectinate unit module, an interpolating unit module and an integral unit module. The invention is characterized in occupying less hardware resource, being applied to higher system clock rate, smaller passband ripple, more stopband attenuation and so on. The invention is applicable to a broadband wireless transceiver, in particular to a wireless broadband transmission system based on OFDM (Orthogonal Frequency Division Multiplexing) in the mobile environment.

The invention relates to a wireless communication carrier tracking method based on FFT-assisted S-PLL. In a high-speed mobile carrier wireless communication system, the carrier tracking method based on a fast Fourier transform-assisted second-order phase-locked loop can solve the problem of large-scale DPP For the wireless communication receiving problem under the condition of Le frequency offset, under the condition that the sampling frequency satisfies the Nyquist sampling theorem, the rough position of the signal frequency is quickly obtained through FFT, and the S-PLL is further used to realize accurate frequency offset estimation. This method makes full use of the frequency offset estimation characteristics of FFT and PLL, can overcome the influence of large-scale Doppler frequency offset and signal noise, and can track large dynamic carrier frequency offset; on the other hand, the method has a simple structure , with lower complexity and stronger practicability.

The invention discloses a specific harmonic cancellation multi-level radio frequency pulse width modulation method in which K odd number of specific harmonic waves are selected, and M-level RF-PWM signals are processed to be equivalent to N 3-level RF-PWM signals with pulse width separately controlled by corresponding comparison thresholds and stacked in a weighted manner, wherein K, M and N are all integers more than 0, N is more than K, and M is equal to 2N+1; N comparison thresholds and corresponding weighting coefficients are controlled in real time according to a normalized envelope signal SA, so that the K specific harmonic wave components of the N 3-level RF-PWM signals has stacked in a weighted manner are mutually counteracted, a base wave component is in direct proportion to the SA, and thus the K specific harmonic waves and integer multiples of odd harmonic waves of the M-level RF-PWM signals are eliminated. Based on the method, the invention also provides a specific harmoniccancellation multi-level radio frequency pulse width modulator. Compared with the prior art, the modulation method and the modulator have the beneficial effects that on the basis that the basic modulation performance is equivalent to the RF-PWM of the same level in the prior art, the suppression requirement on the filter is effectively reduced, the cost and size of the filter are reduced, and thus the comprehensive performance of the wide frequency band DTX is improved.

The invention provides a bilateral CORDIC arithmetic unit, and a parallel Jacobian Hermite matrix characteristic decomposition method and an implementation circuit based on the bilateral CORDIC arithmetic unit. The parallel bilateral CORDIC arithmetic unit is of a six-input and four-output structure. Two times of unilateral CORDIC operation conversion are finished in one-time operation. Meanwhile, the bilateral CORDIC structure can enlarge the angle range of unilateral CORDIC operation from [-pi/2, pi/2) to [-pi, pi) by one time, and reuse of the same circuit structure in the realification process and the diagonalization process of a complex matrix can be possible. The bilateral CORDIC arithmetic unit, and the Hermite matrix characteristic decomposition method and the implementation circuit achieved by utilizing the bilateral CORDIC arithmetic unit can effectively reduce circuit operation time delay, reduce hardware resource consumption and improve operation precision of the circuit through unified factor rectification.

The invention discloses a method for implementing a charge pump keeping constant output current, and the charge pump thereof. The method comprises the following steps of: comparing external input voltage of a charge pump main body circuit with reference voltage, and inputting a comparison result into a clock generating circuit to output corresponding clock oscillation frequency, so that the charge pump main body circuit outputs constant current. The output of the charge pump main body circuit is connected to an enable end of the charge pump main body circuit through a voltage feedback and comparison circuit. The external voltage is dynamically detected, and when the external voltage changes, corresponding clock oscillation frequency can be selected according to the external input voltage,so that the charge pump outputs constant current. Therefore, the output voltage ripple of the charge pump is reduced, and the output voltage stability is improved. The charge pump is simple in implementation mode and structure and low in cost.

The invention provides a FTN (Faster than Nyquist) block transmission method based on DFT (Discrete Fourier Transform), a transmitter, a receiver and a system. Based on DFT and frequency domain windowing technologies, a conventional waveform generating and receiving matched filtering mode based on time domain convolution is equivalently implemented, and then by simple frequency domain equalization, channel multipath interference and self ISI (Inter-symbol interference) are eliminated in steps, so that an implementing structure for base band processing of a transmitting terminal and a receiving terminal is simplified. In addition, by further utilizing high efficiency of DFT calculation, according to the invention, an effect of effectively reducing implementation complexity of the transmitter and the receiver of the system can be achieved.

The invention discloses a button switch structure for elevators, comprising a printed board assembly, a bottom shell part, a button part and a fastener part. The printed board assembly is fixed at the bottom of the bottom shell part, and is used for controlling action of an elevator and emitting light. The bottom shell part includes a first waterproof sealing member and a shell body, the shell body is provided with an inner cavity used for accommodating and fixing the button part, and the shell body is provided with a transparent cover in which a light source of the printed board assembly can be arranged. The button part is used for accepting pressing action of a user and receiving and reflecting light. The fastener part includes a second waterproof sealing member and a fastener body which is nested onto the button part and is connected with the shell body. The first waterproof sealing member is mounted on the contact surface of the bottom shell part and the fastener part, and is used for preventing water flowing in from between the fastener part and the button part from flowing out of the button switch. The second waterproof sealing member is mounted between the fastener part and a switch panel, and is used for preventing water flowing in from the hole of the switch panel from flowing out of the button switch. The button switch structure for elevators has the advantages of simple structure, easy installation and low cost. The button switch structure is waterproof, and the luminescence property and operation hand feel of the button are improved.

The invention discloses a digital pulse width modulator based on IODELAY firmware. The digital pulse width modulator consists of a clock generation module, a synchronous counting module, an IODELAY firmware module and an asynchronous signal generation module. After carrying out frequency multiplication on an input clock signal, the clock generation module generates a basic clock signal and inputs the basic clock signal to the synchronous counting module and the IODELAY firmware module; the synchronous counting module generates a coarse control signal and an initial control signal and respectively inputs the coarse control signal and the initial control signal into the IODELAY firmware module and the asynchronous signal generation module; the IODELAY firmware module carries out delay on the coarse control signal, generates a corresponding termination control signal and then inputs the termination control signal into the asynchronous signal generation module; and in the asynchronous signal generation module, the termination control signal and the initial control signal are processed by an RS trigger to output a final digital pulse width modulation signal. According to the digital pulse width modulator disclosed by the invention, the coarse control signal is subjected to phase delay by the IODELAY module, so that more accurate digital pulse width modulation can be implemented; and the digital pulse width modulator has high accuracy, universality and applicability.

The invention discloses a method for sending messages with random length precisely according to a traffic model. The method generates random numbers within a designated range through a universal PRBS generating circuit and a DSP hardcore resource in FPGA. The random numbers act as the length of to-be-sent messages. Two accumulators are used to perform real-time computing on reciprocal values of the rates of the messages stored in message rate control FIFO in advance to obtain a message interval corresponding to each to-be-sent message. At last, a message sending controller outputs message packaging control enable signals according to requirements of the length of the to-be-sent messages and the message intervals, and precise control of sending rates of the messages with random length according with the given traffic model is achieved. According to the method, the message sending rate can be precisely controlled to a level of a clock period, the achievement is simple, the timing sequence can be converged easily, and the resource usage rate is low.

The invention discloses a power equalization method and a modulator for modulation of a specific harmonic elimination multilevel radio frequency pulse width. The method comprises the steps of: decomposing a specific harmonic elimination multi-level RF-PWM signal into a plurality of 3-level RF-PWM signals with equal pulse areas by using the area equivalence principle based on a multi-level radio frequency pulse signal output from the specific harmonic elimination multi-level RF-PWM, according to the rise and fall of the pulse outputting the multi-level RF-PWM signal; driving a rear-stage SMPA unit, so that multi-level RF-PWM output pulse sequence specific harmonics are eliminated, while achieving the power equalization between the rear-stage SMPA units and between the power tubes in the unit. The radio frequency pulse width modulator is based on the power equalization method, and generates a phase shift control signal for driving a rear-stage 5-level SMPA unit by using a digital delay line unit, thereby realizing active cancellation of a 3X times specific harmonic. The power equalization method for modulation of a specific harmonic elimination multilevel radio frequency pulse widthdoes not need an additional power equalization control circuit, which simplifies the modulator structure.

The invention provides a high-speed parallel OQPSK demodulation clock restoring system which comprises a parallel delay module, a parallel interpolation calculation module, a parallel clock error extraction module, a parallel threshold calculation module and a parallel interpolation coefficient generation module. New 4AR channel parallel Q' channel data are formed after the parallel delay module delays for T/2 to 4AR channel parallel Q channel data in 4AR channel base-band data output by matched filtering. The new 4AR channel parallel Q' channel data and original 4AR channel parallel I channel data are taken into the parallel interpolation calculation module. The obtained 4AR channel data after interpolation are sent to the parallel clock error extraction module to obtain parallel clock errors epsilon T. Meanwhile, the threshold value is obtained by carrying out clock locking indication calculating and integral accumulating on the parallel data after the interpolation, the epsilon T is sent to the parallel interpolation coefficient generation module after parallel low-pass filtering is carried out, and the new generated 4AR channel interpolation coefficient is fed back to the parallel interpolation calculation module. After the threshold reaches a stable value and a clock loop is locked, the parallel interpolation calculation module outputs the maximum value of the data to restore a clock.

The embodiment of the invention provides a clock synchronization method, device and equipment for Internet of Things equipment, and the method comprises the steps: receiving synchronization information transmitted by a cloud server, and recording the first receiving time when the synchronization information is received; determining a time difference between the time of the Internet of Things device and the time of the cloud server; and performing clock synchronization on the Internet of Things device and the cloud server according to the first receiving time and the time difference. The methodcomprises the following steps: recording first receiving time for receiving synchronization information; determining a time difference between the Internet of Things device and a cloud server, performing clock synchronization on the Internet of Things equipment and the cloud server according to the first receiving time and the time difference; the accuracy of clock synchronization of the Internetof Things device and the cloud server can be ensured without adding an additional communication protocol module to the Internet of Things device or enabling the Internet of Things device to communicate with the third-party clock server, the time synchronization requirement of the Internet of Things device is met, and meanwhile, the implementation structure is greatly simplified.

The invention discloses a motor circuit controlling opening and closing of a door or a window or a curtain. The motor circuit comprises a direct-current motor and a direct-current power supply, wherein a current direction switching circuit used for changing the current direction to control forward and reverse rotation of the motor is connected between the direct-current power supply and the direct-current motor, the current direction switching circuit comprises a first relay switching circuit and a second relay switching circuit, the first relay switching circuit controls one input end of the direct-current motor to be connected to one of two output ends of the direct-current power supply, the second relay switching circuit is used for controlling the other input end of the direct-current motor to be connected with the other one of the two output ends of the direct-current power supply, the control signal input end of the first relay switching circuit is connected with a switching-on switch K3 and a travel switch SW1, and the control signal input end of the second relay switching circuit is connected with a switching-off switch K4 and a travel switch SW2. According to the scheme, a motor controller used for controlling forward and reverse rotation of the motor is not adopted, programming and the requirement for match of software and hardware are not needed, and the circuit is simple in structure and easy to implement.