High-speed parallel OQPSK demodulation clock restoring system

A technology for recovering system and clock, applied in the field of communication, can solve problems such as large resource occupation, large number of parallel paths, complex implementation structure, etc.

Active Publication Date: 2013-12-25
XIAN INSTITUE OF SPACE RADIO TECH
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Problems solved by technology

[0010] The phase and clock joint estimation algorithm has good performance, but there is a contradiction between the estimation accuracy and the frequency deviation capture range. At the same time, due to the la

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  • High-speed parallel OQPSK demodulation clock restoring system

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Embodiment Construction

[0036] For the demodulation of high-speed OQPSK signals, limited by the internal processing clock of the device, a parallel clock recovery method is required. Under the condition that the highest frequency of the device remains unchanged, if the single-channel data is processed in N channels in parallel, the demodulation code rate can be increased by N times. Of course, the resources required by the parallel structure relative to the single channel are also correspondingly increased by N times. So this is actually a strategy of exchanging resources for speed.

[0037] In the following, the structure of the parallel clock recovery system of the present invention will be introduced through the functional block diagram of the high-speed parallel digital receiver. Such as image 3 As shown, the intermediate frequency OQPSK modulated signal is demodulated and received by the method of coherent demodulation. First, the high-speed OQPSK modulation signal is converted to an intermed...

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Abstract

The invention provides a high-speed parallel OQPSK demodulation clock restoring system which comprises a parallel delay module, a parallel interpolation calculation module, a parallel clock error extraction module, a parallel threshold calculation module and a parallel interpolation coefficient generation module. New 4AR channel parallel Q' channel data are formed after the parallel delay module delays for T/2 to 4AR channel parallel Q channel data in 4AR channel base-band data output by matched filtering. The new 4AR channel parallel Q' channel data and original 4AR channel parallel I channel data are taken into the parallel interpolation calculation module. The obtained 4AR channel data after interpolation are sent to the parallel clock error extraction module to obtain parallel clock errors epsilon T. Meanwhile, the threshold value is obtained by carrying out clock locking indication calculating and integral accumulating on the parallel data after the interpolation, the epsilon T is sent to the parallel interpolation coefficient generation module after parallel low-pass filtering is carried out, and the new generated 4AR channel interpolation coefficient is fed back to the parallel interpolation calculation module. After the threshold reaches a stable value and a clock loop is locked, the parallel interpolation calculation module outputs the maximum value of the data to restore a clock.

Description

technical field [0001] The invention belongs to the communication field and relates to a high-speed digital demodulator. Background technique [0002] The QPSK modulation method has been widely used in practical systems, but due to its 180° phase shift, after band-limiting processing, a zero-envelope phenomenon may appear. This phenomenon needs to be avoided especially in nonlinear band-limited channels. Although the fluctuation of the envelope can be weakened or eliminated by the nonlinear amplifier, it will expand the spectrum at the same time, and its side lobes will interfere with the signals of adjacent channels, and the band-limited filtering during transmission will be completely useless. Therefore, in actual work, certain processing is usually performed on the QPSK signal to avoid the above-mentioned problems. Offset quadrature phase shift keying OQPSK is one of the better schemes. During quadrature modulation, OQPSK delays the quadrature roadbase band signal rela...

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Application Information

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IPC IPC(8): H04L27/22
Inventor 杨光文易雪燕杨新权匡银李立左金钟
Owner XIAN INSTITUE OF SPACE RADIO TECH
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