Digital pulse width modulator based on IODELAY firmware

Abstract

The invention discloses a digital pulse width modulator based on IODELAY firmware. The digital pulse width modulator consists of a clock generation module, a synchronous counting module, an IODELAY firmware module and an asynchronous signal generation module. After carrying out frequency multiplication on an input clock signal, the clock generation module generates a basic clock signal and inputs the basic clock signal to the synchronous counting module and the IODELAY firmware module; the synchronous counting module generates a coarse control signal and an initial control signal and respectively inputs the coarse control signal and the initial control signal into the IODELAY firmware module and the asynchronous signal generation module; the IODELAY firmware module carries out delay on the coarse control signal, generates a corresponding termination control signal and then inputs the termination control signal into the asynchronous signal generation module; and in the asynchronous signal generation module, the termination control signal and the initial control signal are processed by an RS trigger to output a final digital pulse width modulation signal. According to the digital pulse width modulator disclosed by the invention, the coarse control signal is subjected to phase delay by the IODELAY module, so that more accurate digital pulse width modulation can be implemented; and the digital pulse width modulator has high accuracy, universality and applicability.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a digital pulse width modulation circuit. Background technique [0002] In the system structure using digital pulse width modulation (Digital Pulse Width Modulation, DPWM), the main methods currently used are hybrid DPWM (Hybrid DPWM), and the second is DPWM realized by Dither method. The DPWM implemented by the Dither method is mainly realized by the idea of ​​​​the design. This design can use a low-precision and high-frequency DPWM to achieve a high effective output accuracy, which also reduces the power consumption and area of ​​​​the DPWM. However, the DPWM realized by the Dither method will generate a cycle delay when the mode is switched, which is not good for the high-speed response of the DPWM. Hybrid DPWM designs have no unwanted delays. [0003] The hybrid DPWM combines the traditional counter structure and the delay chain structure, and is usually com...

AI Technical Summary

Problems solved by technology

However, this method has the following disadvantages: the basic clock frequency of this method can only reach 1MHz, and with the increase of the basic clock frequency, this method cannot meet the requirement

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