2results about How to "Reduce operation delay" patented technology

This utility model relates to the field of parts cleaning technology and discloses a rotary metal parts cleaning device, including a workbench. A protective box is fixedly installed on the upper surface of the workbench, and an installation plate is fixedly installed on the rear inner wall of the protective box. The upper surface of the workbench is open. Two round rods are fixedly installed on the front and rear inner walls of the workbench, and the two round rods are installed in a left-right correspondence. An auxiliary mechanism is set on the workbench. The auxiliary mechanism includes an installation block and a tightening plate. By allowing the installation block to slide back and forth along the round rods, the turntable can be moved out of the cleaning area inside the protective box when changing parts, avoiding obstruction by the equipment shell and spray head, reducing the chance of contact between the operator and the moving parts inside the equipment, providing a more open operating space for the operator, making it more convenient to load and unload parts, reducing operational delays caused by obstruction, facilitating the replacement of metal parts by the operator, and improving the efficiency of metal parts replacement.

The application discloses a memory operation system compliant with DDR memory access timing, and belongs to the field of memory and scientific calculation, comprising: a row-level parallelism driven timing termination mechanism, which utilizes row nonlinear charging characteristics to reduce tail delay of tRCD and tRP; and a row block interleaving, row-column collaborative vector-matrix multiplication (VMM) access mechanism, which reduces tRAS and overlaps CL timing parameters without increasing peripheral column ADC precision overhead, and reduces cross-point RAM internal core delay; the proposed row access and column access collaborative optimization memory hardware design can enable VMM operation compliant with DDR memory access timing in a memory-centric manner, so as to realize efficient hardware execution of low-delay, high-bit-width data-intensive scientific calculation (computational physics) loads.